systemC synthesis guidlines

[mohitnegi]

hi everyone ,

 

Is there any synthesis guidlines for systemC ???

 

and what does ESL and HSL means ...???

 

thanks

Mohit

[Hans64]

Hi Mohit,

 

See,

 

http://www.accellera.org/activities/committees/systemc-synthesis/

http://en.wikipedia.org/wiki/Electronic_system-level_design_and_verification

 

HLS is High Level Synthesis,

 

Hans.

www.ht-lab.com

 

[Hans64]

Hi Mohit,

 

See,

 

http://www.accellera.org/activities/committees/systemc-synthesis/

http://en.wikipedia.org/wiki/Electronic_system-level_design_and_verification

 

HLS is High Level Synthesis,

 

Hans.

www.ht-lab.com

 

[mohitnegi]

Hi Hans,

Thanks for your prompt response ...

 

reading the above links is it true that HLS and ESL are same ......

 

and about sythesis of systemC is there any list of keyword available ......

and any open source systemC tool for synthesis .....

 

thanks

Mohit

[apfitch]

ESL is not the same as HLS. ESL refers to all Electronic System Level activities (virtual prototyping, system modelling, algorithm development, model-based design, HLS).

 

HLS refers specifically to synthesis.

 

As Hans said, the link describing synthesis in SystemC is here:

http://www.accellera...temc-synthesis/

 

I'm not sure what you mean by "list of keyword". SystemC is C++, C++ keywords are SystemC keywords.

 

I'm not aware of any open source synthesis, though some people have translated RTL SystemC code into Verilog, then used a standard Verilog RTL synthesis tool,

 

regards

Alan

[mohitnegi]

hi Alan,

 

what about OSCI reference simulator ....given at

http://en.wikipedia.org/wiki/SystemC

 

what i meant by list of synthesizable keyword is like in verilog we have

"for" cannot be synthesized ...Is there anything lie this in systemC...

 

thanks...

Mohit Negi

[apfitch]

The things that can be synthesized are described in the document Hans mentioned.

 

regards

Alan

 

P.S. "for" can be synthesized in Verilog, even in RTL tools (as long as the number of repeats is static).

[mohitnegi]

thanks Alan and Hans for your quck response ....

[mohitnegi]

hi ,

Hey i have heard about proof of concept simulator which is open source ...

where can i get it ...

 

thanks ..

[apfitch]

http://www.accellera.org/downloads/standards/systemc

 

Alan

[mohitnegi]

hi ,

while reading the doc .....ESL=Architecture synthesis + HSL ....

 

where Architecture synthesis means it reads architecure described using TLM libraries and decide memory infrastructure, cache structure,

DMA structure, bus layer , i/o devices and CPU selection .....

my doubt is how it does this ....(are all these done by the tool)....

then HSL includes description of module behaviour, i/o actions, computation functionality and other input of HSL is

the target tech library and the list of directives.....then a state m/c is generated which specify the datapath implemenation

of the desired func...these are in RTL codes...

now this all this has confused me ......

 

could anyone pls simplfy it ....

 

thanks...

mohit

[apfitch]

The short answer is probably "no we can't simplify it" :-) If you want to learn about high level synthesis, you need to a bit of reading. You could start with the Wikipedia article on High Level Synthesis

 

https://en.wikipedia.org/wiki/High-level_synthesis

 

and then there's some useful background information on Forte DS website

 

http://www.forteds.com/behavioralsynthesis/

 

It might be worth reading the documenation on Vivado HLS (www.xilinx.com) as well, there is some introductory material, for instance this video: http://www.xilinx.com/training/vivado/vivado-hls-in-depth-technical-overview.htm

 

One thing to remember with HLS is that it is not as mature as RTL, so different tools may well have different approaches,

 

regards

Alan

 

Try reading those and see if that helps,

 

kind regards

Alan

[foster911]

LegUp 2.0 (an open source high-level synthesis tool)
...............
http://legup.eecg.utoronto.ca/download.php
http://legup.eecg.utoronto.ca/demo.php
or
http://legup.eecg.utoronto.ca/getstarted.php
....................
About the above demo:
The LegUp 2.0 demo will synthesize your C code into Verilog RTL running entirely in hardware (no soft TigerMIPS co-processor). The demo uses the default LegUp settings: Cyclone II FPGA target device, 15ns period constraint, binding enabled for dividers, and pattern sharing enabled. The default code is the MIPS benchmark from CHStone, which implements a MIPS processor and then executes a short MIPS program to sort an 8 integer array.
...................
A good thesis for better learning:
Enabling Hardware/Software Co-design in High-level Synthesis
https://tspace.library.utoronto.ca/bitstream/1807/33380/4/choi_jongsok_201211_MASc_thesis.pdf

 

 

The HercuLeS high-level synthesis tool:
http://www.nkavvadias.com/hercules/

[mohitnegi]

hello guys ,,,

 

thanks for your prompt response ....

as reading articles on systemC synthesis .... i have a few  basic ques ...

 

1.why do we require systemC synthesis when we already have HDL synthesis ....

3.if system C synthesis is still n draft version how come tool already developed for it ...

 2.Is it that systemC synthesis tool are interoperable ....(i.e keyword synthesized on one HLS tool could generate different output then other tool)

3. And if we wish to do synthesis of a systemC model we have first convert it into a synthesizable systemC model(i.e remove all the

constructs or keywords that cannot be synthesized)...

 

 

thanks ....

[apfitch]

Hi Mohit,

  1. The important issue is not the language, but the technology. Behavioural synthesis tools generally deduce a combination of state machines (for control) and datapath (for signal processing). The key thing is that you as a designer do not have to write the micro-architecture yourself. Hence behavioural synthesis is potentially more productive than standard RTL synthesis.

That argument is language independent. A behavioural VHDL tool would be more productive than an RTL VHDL tool. Writing RTL in SystemC would be no more productive than writing RTL in VHDL or Verilog.

 

So  your question "why do we require SystemC sythesis when we have HDL synthesis" would be better as "why do we need behavioural synthesis rather than RTL synthesis". And the answer is you only need it if it's better for you in some way (faster time-to-market for instance). No-one is forcing you to use behavioural synthesis :-)

 

2. I don't know if SystemC synthesis tools are interoperable.

 

3. How come tools exist even though the synthesis standard is a draft?

EDA vendors are free to ignore standards :-) Standards only get adopted (and developed) if EDA vendors and users can see value in those standards. So I guess no-one is motivated to finish the synthesis standard.

 

The key thing about the synthesis standard (as opposed to a language standard) is it's trying to guide how a tool may interpret SystemC code. EDA vendors see that as a legitimate area of product differentiation.

 

The same thing happened with VHDL 1076.6 - the vendors essentially ignored it.

 

 

4. You may mix synthesisable and non-synthesisable code, you just have to hide the code using the pre-processor or meta-comments.

The same is true in VHDL and Verilog - you can include non-syntheisable code, but it is typically hidden using meta-comments, e.g.

-- synthesis translate_off

   code that won't synthesize goes here

-- synthesis translate_on

 

regards

 

Alan

[mohitnegi]

Hello ,

 

Thanks for your reply Alan ....

 

i have another question ...i have read that with the help of systemC ..now hardware software partioning is possble at higher

abstraction .....to which i fail to understand how it is done and what was the earlier appoarch for hw/sw partioning ....

 

Thanks

Mohit Negi

[foster911]

There are 2 tedious tasks in the field of ESL and SOC:

1- Microprocessor model creation and Compiler and Driver development

2- Hardware/Software partitioning and interfacing them together.

 

For the second part, please read below DOC. It's not related to SystemC but can reveal lots of ambiguities.

 

Hardware(Verilog or VHDL)/Software(C or assembly)/Micro-processor tuning and mixing

http://depositfiles.com/files/grlag48ee

[apfitch]

There companies with tools to assist with H/W S/W partitioning. A couple I've heard of are Gedae and Cofluent Design - it might be worth having a look at their websites,

 

regards

Alan