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accessing a generate block hierarchy

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Hi all,
I'm trying to access a verilog hierarchy which was generated by a generate block - but I'm having some problems with it. for example:

verilog file: (let's assume it is located at "testbench" hierarchy, and an interface named "some_interface" is already defined)

genvar i;
for (i=0;i<3;i++)
some_interface some_interface_inst(clk);
assign some_interface_inst.x=1'b0;
assign some_interface_inst.y=1'b1;



systemverilog file:

virtual some_interface some_interface_arr[0:2];

for (int i=0;i<3;i++)

I believe I can't access a generated verilog hierarchy with a system-verilog for loop (variable i). Am I correct? and if so - is there a way to pass this obstacle?
Thanks in advance,
P.s - What I'm generally trying to do is to get handles to the instantiated interfaces (some_interface) and pass them to system verilog objects in my testbench, using the virtual interface array.

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