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UVM simulation phases

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I have created pre_reset and pre_configure phase in my test.

I have not registered any sequence for pre_reset and pre_configure phase but I have some delay in my pre_reset phase of the test.

Still i see both pre_reset and pre_configure phases starting at 0 time. why is it so?


Example below shows what I mean to say but it is not comple clean code.


class my test extends uvm_test;


// registration


virtual tast pre_reset (uvm_phase phase);

  $display(in pre_rest phase);


  top.rst = 0;


 top.rst = 1;



virtual task pre_configure(uvm_phase phase);

  $display(in pre_configure phase);

  top.interrupt_en = 1;



here both messaged in pre_reset phase and in pre_configure phase are coming at 0 time only.

What I understood is pre_configure phase will be executed after pre_reset, reset and post_reset phase are over. so message in pre_configure should come after 200 timestamp only if I dont have anything for reset and post reset pahse.


Please correct me if I am wrong.

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unless you raise an objection to prevent the phase from ending all your started functionality in pre_reset,pre_configure is terminated instantly. so you have to wrap all functionality which should be atomic / not interrupted or terminated in phase.raise_objection() and phase.drop_objection()



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