Having Power Aware and Performance verification component integrated

[Rakesh]

Hi All,

 

I am new to UVM methodology. I have gone through UVM class reference manual. As, UVM is an open source method used by whole verification industry, Run time performance verification and power aware verification can be standardize with providing components for those verification in library.

 

Performance measurment can be standardize for bandwidth utilization, effective throughput and internal delay calculation. It can be both combination of checker component calcualtion at run time and timers to calculate the difference between start and stop timers to calculate bandwidth in Transfers/Second.

 

Also, Nice reporting table can be added for generating performace reporting for all buses at one place.

 

People can inherrit the base class and modify the usage as needed.

 

Regards,

Rakesh Sachdev

[uwes]

here is some info howto do that

 

http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:doc;src=wp;q=ApplicationNotes/Functional_Verification/OVM_UVM_AppNotes/Performance_Analysis_with_UVM.pdf

 

 

/uwe