Setup and Hold Time checks in SystemC

[jayakirthi]

Hi,

I need to make a timing checks for the input signals of a module (e.g., check set-up and hold times are not violated, check Pulse width). Is there any method which would let me do this. If further information is needed, please contact me!

Thank you in advance for your help.

[kocha]

Hi, jayakirthi

 

Why need a timing checks SystemC model?

 

I think it unnecessary to perform a timing check by SystemC. 

However, when generating RTL using a High Level Synthesis tool, it needs to be conscious of timing, but it is it.

I am corresponding with a tool and think that it is not necessary to correspond language. 

 

Regards,

Kocha

[apfitch]

Just use sc_time_stamp() to retrieve the times at the points you're interested in, then compare the difference in time stamps to your spec,

 

regards

Alan

[jayakirthi]

Just use sc_time_stamp() to retrieve the times at the points you're interested in, then compare the difference in time stamps to your spec,

 

regards

Alan

Thank you sir... Now i am using same technique..

But is there any direct function to check it ( like $setup in Verilog/SystemVerilog).. 

Thanks..

[jayakirthi]

Hi, jayakirthi

 

Why need a timing checks SystemC model?

 

I think it unnecessary to perform a timing check by SystemC. 

However, when generating RTL using a High Level Synthesis tool, it needs to be conscious of timing, but it is it.

I am corresponding with a tool and think that it is not necessary to correspond language. 

 

Regards,

Kocha

Thanks for the reply...

i was working on a project where i need to check such things on SystemC side.. So..

[apfitch]

No there's nothing like $setup in SystemC. SystemC is used by most people for transaction level modeling, and also for high level synthesis.

 

If you want to do things that are directly supported in Verilog or VHDL, you may be better off using Verilog or VHDL,

 

kind regards

Alan

[jayakirthi]

No there's nothing like $setup in SystemC. SystemC is used by most people for transaction level modeling, and also for high level synthesis.

 

If you want to do things that are directly supported in Verilog or VHDL, you may be better off using Verilog or VHDL,

 

kind regards

Alan

 

 Thank you..