abhineet2210 Posted February 25, 2013 Report Posted February 25, 2013 does any one has idea about the SystemC models can be verified using SV/UVM methodology ? Quote
GuyM Posted February 25, 2013 Report Posted February 25, 2013 Absolutely yes, SystemC models can be verified by UVM-SV (and also integrated with UVM testbenches). Cadence recommends doing this with the enhancements provided by UVM-ML. You can see a general overview on this and more in previous Cadence webinars here: 1. UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar Overview in: http://www.cadence.com/Community/blogs/fv/archive/2012/10/11/uvm-systemverilog-in-a-multi-language-soc-world-uvm-ml-webinar. Archived in: http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=686 2. Bringing SystemC and C/C++ Models into UVM Overview in: http://www.cadence.com/Community/blogs/ii/archive/2011/11/07/archived-webinar-bringing-systemc-and-c-c-models-into-uvm.aspx Archived in: http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=558 You can find more information in contributions available on UVMworld: 3. The enabling library: UVM-ML Version 1.1: http://www.uvmworld.org/contributions-details.php?id=98&keywords=UVM_ML 4. An elaborate usage example: UVM Reference Flow Version 1.1: http://www.uvmworld.org/contributions-details.php?id=105&keywords=UVM_Reference_Flow_Version_1.1 Guy Quote
Hash Posted February 25, 2013 Report Posted February 25, 2013 Believe SystemC models are connected to SV/UVM by TLM Thanks Guy , nice information Quote
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