fbochud Posted February 8, 2013 Report Share Posted February 8, 2013 Hi, I am trying to use a register model from a virtual sequencer. The system looks like this: tb_env |- virtual sequencer | |- registerbus sequencer | |- stream sequencer | |- model | |- registerbus model | |- scoreboard | |- registerbus agent | |- sequencer | |- driver, monitor | |- stream agent | |- sequencer, driver, monitor My problem is that I don't know how to "map" the local model with the actual model in the sequence library. I get a "Error-[NOA] Null object access" when running the register bus sequence tb_reqbus_seq (cf source code under). How can I refer to my registermodel that is instantiated in model? Can somebody helps! Thanks Florian Here is the source for my sequences / virtual sequence and virtual sequencer: class tb_regbus_seq extends uvm_reg_sequence; function new(string name="tb_regbus_seq"); super.new(name); endfunction : new `uvm_object_utils(tb_regbus_seq) virtual task body(); ral_block_tb_memmap model; uvm_status_e status; $cast(model, this.model); model.myreg.write(status, 7, .parent(this)); // Error-[NOA] Null object access !!! endtask : body endclass : tb_regbus_seq // virtual sequencer // cf UVM 1.1 Userâ€™s Guide ch. 4.8.1: class tb_virtual_sequencer extends uvm_sequencer; `uvm_component_utils(tb_virtual_sequencer) uvm_sequencer#(regbus_transfer) regbus_sqr; uvm_sequencer#(stream_transfer) stream_sqr; function new (string name = "tb_virtual_sequencer", uvm_component parent); super.new(name, parent); endfunction : new endclass : tb_virtual_sequencer // Declare virtual sequence and sequencer // UVM 1.1 Userâ€™s Guide ch. 4.8.2: class tb_vseq extends uvm_sequence; `uvm_object_utils(tb_vseq) `uvm_declare_p_sequencer(tb_virtual_sequencer) tb_regbus_seq my_regbus_seq; tb_stream_seq my_ stream_seq; virtual task body(); `uvm_do_on(my_regbus_seq, p_sequencer.regbus_sqr); `uvm_do_on(my_stream_seq, p_sequencer.stream_sqr); endtask : body endclass : tb_vseq In addition the virtual register bus sequencer is connected to the register bus sequencer in tb_env / connect_phase, as described in UVM 1.1 Userâ€™s Guide ch. 4.8.4.a): v_sqr.regbus_sqr = regbus.sqr; My register model has been generated from a ralf file and connected as described in UVM user guide 126.96.36.199 Quote Link to comment Share on other sites More sharing options...
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