How to use a register model from a virtual sequencer?

[fbochud]

Hi,

I am trying to use a register model from a virtual sequencer.

The system looks like this:

tb_env

|- virtual sequencer

| |- registerbus sequencer

| |- stream sequencer

|

|- model

| |- registerbus model

|

|- scoreboard

|

|- registerbus agent

| |- sequencer

| |- driver, monitor

|

|- stream agent

| |- sequencer, driver, monitor

My problem is that I don't know how to "map" the local model with the actual model in the sequence library. I get a "Error-[NOA] Null object access" when running the register bus sequence tb_reqbus_seq (cf source code under). How can I refer to my registermodel that is instantiated in model? Can somebody helps!

Thanks

Florian

Here is the source for my sequences / virtual sequence and virtual sequencer:

class tb_regbus_seq extends uvm_reg_sequence;

function new(string name="tb_regbus_seq");

super.new(name);

endfunction : new

`uvm_object_utils(tb_regbus_seq)

virtual task body();

ral_block_tb_memmap model;

uvm_status_e status;

$cast(model, this.model);

model.myreg.write(status, 7, .parent(this)); // Error-[NOA] Null object access !!!

endtask : body

endclass : tb_regbus_seq

// virtual sequencer

// cf UVM 1.1 User’s Guide ch. 4.8.1:

class tb_virtual_sequencer extends uvm_sequencer;

`uvm_component_utils(tb_virtual_sequencer)

uvm_sequencer#(regbus_transfer) regbus_sqr;

uvm_sequencer#(stream_transfer) stream_sqr;

function new (string name = "tb_virtual_sequencer", uvm_component parent);

super.new(name, parent);

endfunction : new

endclass : tb_virtual_sequencer

// Declare virtual sequence and sequencer

// UVM 1.1 User’s Guide ch. 4.8.2:

class tb_vseq extends uvm_sequence;

`uvm_object_utils(tb_vseq)

`uvm_declare_p_sequencer(tb_virtual_sequencer)

tb_regbus_seq my_regbus_seq;

tb_stream_seq my_ stream_seq;

virtual task body();

`uvm_do_on(my_regbus_seq, p_sequencer.regbus_sqr);

`uvm_do_on(my_stream_seq, p_sequencer.stream_sqr);

endtask : body

endclass : tb_vseq

In addition the virtual register bus sequencer is connected to the register bus sequencer in tb_env / connect_phase, as described in UVM 1.1 User’s Guide ch. 4.8.4.a):

v_sqr.regbus_sqr = regbus.sqr;

My register model has been generated from a ralf file and connected as described in UVM user guide 5.9.2.1

[fbochud]

What I am basically trying to do is to have a sequence where I can sequentially set the register of my dut via its register interface, followed by starting a video stream via another dut interface.

It looks like using a virtual sequencer is the way to go, but there might be other way to do this?

[fbochud]

I think I am a bit further: the adapter in the environment should be connected to the regbus_sequencer in the virtual sequencer instead of the regbus agent sequencer:

class tb_env extends uvm_env;

[...]

function void connect_phase(uvm_phase phase);

if (model.regbus_model.get_parent() == null) begin

reg2avm_adapter reg2avm = new;

model.regbus_model.default_map.set_sequencer(v_sqr.regbus_sqr,reg2avm); // instead of model.regbus_model.default_map.set_sequencer(regbus.sqr,reg2avm)

model.regbus_model.default_map.set_auto_predict(1);

end

// Connect Sequencer to virtual Sequencer

v_sqr.regbus_sqr = regbus.sqr;

v_sqr.stream_sqr = source[0].sequencer;

endfunction : connect_phase

[...]

endclass : tb_env

But now, I am getting an error a bit further: [REG_NULL_SQR] Null reference specified for bus sequencer

Can it be that the virtual sequencer is not mapping the register model when running:

`uvm_do_on(my_regbus_seq, p_sequencer.regbus_sqr);

?

Any ideas?

Edited February 19, 2013 by fbochud

[fbochud]

Ok, here is what I did to make it work (with help of the support of our simulator vendor)

- ignore my previous comment (#3, no update in tb_env)

if (model.regbus_model.get_parent() == null) begin

reg2avm_adapter reg2avm = new;

model.regbus_model.default_map.set_sequencer(regbus.sqr,reg2avm)

model.regbus_model.default_map.set_auto_predict(1);

end

- set register model in resource database in my model class:

uvm_resource_db#(uvm_reg_block)::set("MODEL","regmodel",regbus_model);

- get the register model from the resource database in the virtual sequence and assign it to the sequence:

class tb_vseq extends uvm_sequence;

`uvm_object_utils(tb_vseq)

`uvm_declare_p_sequencer(tb_virtual_sequencer)

tb_regbus_seq my_regbus_seq;

tb_stream_seq my_ stream_seq;

virtual task body();

uvm_reg_block model;

uvm_resource_db#(uvm_reg_block)::read_by_name("MODEL","regmodel", model);

my_regbus_seq = tb_regbus_seq::type_id::create();

my_regbus_seq.model = model;

my_regbus_seq.start(null);

`uvm_do_on(my_stream_seq, p_sequencer.stream_sqr);

endtask : body

endclass : tb_vseq

Hope it helps

[aravind787]

Hi,

 

Thanks for solution. This method worked for me