ssingh Posted February 7, 2013 Report Share Posted February 7, 2013 I am doing design and verification with systemverilog. My UVM environment has all input data arrays in sequence item as of type 'bit'. My design uses the type 'logic'. It is allowed in systemverilog to assign bit type to logic type and vice versa. But I still get the error: Connection type 'bit[15:0]$[5569:0]' is incompatible with 'reg[15:0]$[5569:0]' for port (input_row_1): Array elems. must both be 2-state or 4-state. Why does this happen? Quote Link to comment Share on other sites More sharing options...
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