swapnilm Posted January 21, 2013 Report Share Posted January 21, 2013 Dear All, Can anyone plz guide me through the commands to run in simulator, in ready to go example from systemverilog.in (uvm example)? I am getting lots of errors. I am using questasim 10.0b with uvm-1.0p1 library. Help would be appreciated. Thanks Quote Link to comment Share on other sites More sharing options...
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