Jump to content

Error-[SE] Syntax error

Recommended Posts

In my env I am using vcs2012.09-Beta3 and uvm1.1b-0. I got following compilation error.

Error-[sE] Syntax error

Following verilog source has syntax error :

"/tool/pandora64/.package/uvmkit-1.1b-0/uvm/src/tlm1/uvm_sqr_ifs.svh", 37:

token is 'uvm_object'

virtual class uvm_sqr_if_base #(type T1=uvm_object, T2=T1);

Thanks in advance

Link to comment
Share on other sites

Please do not use Beta Software.

VCS2012.09-3 is the latest version and you should switch to it immediately.

First ensure your testbench works by using vcs "-ntb_opts uvm " switches, then you can enable your own or UVM-1.1b version by using setenv VCS_UVM_HOME /tool/pandora64/.package/uvmkit-1.1b-0/uvm/src

If you still see an issue then email the compilation logfile to vcs_support@synopsys.com


Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...