use read_reg and peek_reg

[mrforever]

Hi all,

There is one problem about using read_reg(frontdoor way) and peek_reg(backdoor way) disturbing me. There is one WO register to verify.

My way as follow:

write_reg(reg_block_usrqp.usr_qp_ctrl_r.recv_fc_r, status, data);

peek_reg(reg_block_usrqp.usr_qp_ctrl_r.recv_fc_r, status, rd_data);

Then vcs reports such UVM_ERRORs:

UVM_ERROR /EDA_Tools/synopsys/vcs_G-2012.09/etc/uvm-1.1/uvm-1.1c/src/reg/uvm_reg_block.svh(2049) @ 12: reporter [RegModel] Block does not have hdl path defined for abstraction 'RTL'

UVM_ERROR: get: unable to locate hdl path usr_qp_ctrl_r[ 0].recv_fc_r

Either the name is incorrect, or you may not have PLI/ACC visibility to that name

When i change peek_reg to read_reg, the UVM_ERRORs disappear.

By the way, if i do like this.

poke_reg(reg_block_usrqp.usr_qp_ctrl_r.recv_fc_r, status, data);

peek_reg(reg_block_usrqp.usr_qp_ctrl_r.recv_fc_r, status, rd_data);

Then vcs reports such UVM_ERRORs:

UVM_ERROR: set: unable to locate hdl path (usr_qp_ctrl_r[ 0].recv_fc_r)

Either the name is incorrect, or you may not have PLI/ACC visibility to that name

UVM_ERROR /EDA_Tools/synopsys/vcs_G-2012.09/etc/uvm-1.1/uvm-1.1c/src/reg/uvm_reg_block.svh(2049) @ 12: reporter [RegModel] Block does not have hdl path defined for abstraction 'RTL'

UVM_ERROR: get: unable to locate hdl path usr_qp_ctrl_r[ 0].recv_fc_r

Either the name is incorrect, or you may not have PLI/ACC visibility to that name

my vcs script has already included +acc +api options. Should I give the full hdl path including DUV?

Did anybody run into the same problem? Please give me some help if you did. Thanks in advance.

Regards

mrforever

Edited January 8, 2013 by mrforever

[amitshere]

Are you generating your register Model from RALF using ralgen?

Have you provided the 'hdl paths' in the RALF specification? If not , you would have to do that.

The user documentation in VCS "UVM Register Abstraction Layer Generator User Guide" has the details in the chapter: "Generated Backdoors"

[mrforever]

Hi amit,

Thanks for your reply. I will have a look at the “UVM Register Abstraction Layer Generator User Guide”