GiuseppeDiGuglielmo Posted January 30, 2013 Report Share Posted January 30, 2013 Dear all, up to my knowledge, there are two main verification environments/libraries/methodologies for SystemC (and SystemC TLM). That is SystemC Verification Environment (SCV) and SystemC UVM from Cadence. SCV development stopped in 2006. Do you know what is the current status of the Verification Group? Is there any plan of further improvements? UVM, w.r.t. SCV, is a more robust methodology but still SystemC UVM provided by Cadence is a "Prodigal Son" if compared with the SystemVerilog support of UVM. Are you aware of any other solution for verification of SystemC designs? SCV and SystemC UVM are simulation based approaches? Do you know any available formal-technique-based verification tool for SystemC (e.g., a model checker)? Thanks! Quote Link to comment Share on other sites More sharing options...
dakupoto Posted January 31, 2013 Report Share Posted January 31, 2013 Hello Sir, There is a UVM conference/seminar on right now at Austin, Texas. You might want to check out the proceedings to see what the gurus have to say right now. Quote Link to comment Share on other sites More sharing options...
GiuseppeDiGuglielmo Posted January 31, 2013 Author Report Share Posted January 31, 2013 Hi, do you have any link? Quote Link to comment Share on other sites More sharing options...
Hans64 Posted January 31, 2013 Report Share Posted January 31, 2013 There is a SystemC VMM class library (VMM came before OVM which came before UVM which will probably be replaced again soon by another acronym .....) I believe SCV is still being looked at but constraint solvers are complex pieces of technology combine this with non-perfect C++ introspection and you have a complex task at hand. From what I have heard Cadence continues to maintain and update SCV commercially (for NCsim), so what we need is for some of their engineers to have a look at the current SCV version and bring it back to live ;-) Hans. www.ht-lab.com PS I would not compare UVM with SCV as they are quite different. UVM is a Verification framework whereas SCV is more of a verification toolbox. maehne 1 Quote Link to comment Share on other sites More sharing options...
GiuseppeDiGuglielmo Posted January 31, 2013 Author Report Share Posted January 31, 2013 Hi Hans, There is a SystemC VMM class library (VMM came before OVM which came before UVM which will probably be replaced again soon by another acronym .....) I am aware of that. This is an image that I use in my presentations: I believe SCV is still being looked at but constraint solvers are complex pieces of technology combine this with non-perfect C++ introspection and you have a complex task at hand. Yes. SCV is definitely complex for people who are used to Verilog or VHDL but not C++. The introspection/extension stuff could be "cumbersome" sometimes. From what I have heard Cadence continues to maintain and update SCV commercially (for NCsim), so what we need is for some of their engineers to have a look at the current SCV version and bring it back to live ;-) I am using Cadence NCsim. I will check if any difference exist between SCV 2006 (Accellera) and the Cadence SCV. Most likely Cadence guys are just supporting the latest GNU g++ compiler, as I did (some patches and still a lot of warnings in compilation). PS I would not compare UVM with SCV as they are quite different. UVM is a Verification framework whereas SCV is more of a verification toolbox. Yes indeed. I consider SCV just a library (let's call it a toolbox) and UVM a methodology. But I am not sure if in UVM I can use SCV or if SCV is deprecated and I have to use e language. What do you think? Quote Link to comment Share on other sites More sharing options...
apfitch Posted February 2, 2013 Report Share Posted February 2, 2013 For a long time the Verification Working Group was moribund, but it is now alive again - you can join it here: http://www.accellera.org/activities/committees/systemc-verification Cadence's version did have significant enhancements, including coverage classes, event operators, and more constraint operators. regards Alan Quote Link to comment Share on other sites More sharing options...
GiuseppeDiGuglielmo Posted February 3, 2013 Author Report Share Posted February 3, 2013 Hello Alan, I am not able to join the group. The authentication form does not let me in. The group page says: Join this Working Group If you are an employee of a member company and would like to join this working group,click here (requires login) and click Join Group. WG participation requires right of entry by the group chair. I am a researcher at Columbia University, not a employee of a member company. Can I join the group too? Quote Link to comment Share on other sites More sharing options...
apfitch Posted February 4, 2013 Report Share Posted February 4, 2013 Hi Guiseppe, you can register with the Accellera website (it has a separate registration from these forums). Once you're registered, I think you can join the group as an observer (a non-voting member), as long as the group chair approves you. I hope what I've said is true! kind regards Alan Quote Link to comment Share on other sites More sharing options...
jeromecornetst Posted February 7, 2013 Report Share Posted February 7, 2013 Hi Guiseppe, we are indeed working toward a new "maintenance" update of scv which will brings compatibility with more recent systems (64-bit, etc.). Working group members are also investigating new requirements and possibilities for an bigger update. Meanwhile, you may want to check the CRAVE and SCIVER libraries: http://www.systemc-verification.org which brings several improvements over the existing SCV code. Best regards, Jerome Quote Link to comment Share on other sites More sharing options...
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