rakeshanigundi

Here I am trying to first create the user defined sequence "seq_lib" assign it to default sequence and then my call super.build_phase(phase) creates the tb/sequencer etc.. I did this after reading in some UVM book.. Are you saying this is not the correct procedure? It would be helpful if you elaborate on your above comment. In the user defined "seq_lib" I do have raise and drop objections defined in the pre_body and post_body. In the testcase itself I have one more objections defined in run_phase (not sure if I need this)

Hello Folks, I am new to UVM and trying to contruct a simple testbench with user defined sequences and sequence libraries. In my sample testcase's build_phase I have function void build_phase(uvm_phase phase) ; vmidmt_client_seq_base seq_lib ; seq_lib = vmidmt_client_seq_base::type_id::create("seq_lib", this) ; uvm_config_seq::set(this, "*","default_sequence", seq_lib) ; uvm_config_int::set(this, "*","min_random_count", 100) ; uvm_config_int::set(this, "*","man_random_count", 100) ; super.build_phase(phase) ; uvm_report_info(get_name()," vmidmt_test_seq_lib build phase complete") ; endfunction : build_phase Here vmidmt_client_seq_base is simple user defined sequence with run_phase as task vmidmt_client_seq_base::body() ; `uvm_do(req); endtask : body In the run_phase of the testcase I have simple raise and drop objections as below task vmidmt_test_seq_lib::run_phase(uvm_phase phase) ; super.run_phase(phase) ; #300; uvm_report_info(get_name(), "Raising objection") ; phase.raise_objection(this) ; #30000; uvm_report_info(get_name(), "Dropping objection") ; phase.drop_objection(this) ; uvm_report_info(get_name(), "Test should be done whenever stimulus finishes") ; endtask : run_phase I get the below error when I run the testcase (run time error) # UVM_FATAL @ 0: uvm_test_top.tb.vmidmt_client_master.seq@@seq_lib [sEQ_NOT_DONE] Sequence uvm_test_top.tb.vmidmt_client_master.seq.seq_lib already started Any debug tips or suggestions on what I might be doing wrong is really appreciated. What does the SEQ_NOT_DONE error actually mean? Thanks Rakesh

Hi Kathleen, Thanks a tonne.. You suggestion of making initial begin uvm_config_db#(virtual core_if)::set(null, "*", "core_vif", core_intf); run_test(); end Worked for me.. -Rakesh

LKB, thanks a lot for the reply My Bad.. I think I made a mistake while I was typing out the message, the line in my top_tb.sv which is giving the error looks like below uvm_config_db#(virtual interface core_if)::set(null, "*core_if", "core_if", core_intf) ; NOT uvm_config_db#(virtual vmidmt_if)::set(null, "*core_if", "core_if", core_intf) ; So by specifiying uvm_config_db#(virtual interface core_if) , the compiler should now know that core_if is virtual interface which has been included in my top_tb.sv Snippet from my top_tb.sv `include "uvm_macros.svh" `include "core_if.sv" `include "core_sv_defines.sv" `timescale 1ns/1ps module tb_top; import uvm_pkg::*; import quvm_addons_pkg::*; import core_test_pkg::* ; . . singal declarations . . // core_if is a virtual interface which is included in the file core_if.sv core_if core_intf ( .core_client_clk (core_client_clk), .core_config_clk (core_config_clk) ); // Register the interface with factory uvm_config_db#(virtual interface core_if)::set(null, "*core_if", "core_vif", core_intf) ; Above line is giving me the error as ../ top_tb.sv(82): near "(": syntax error, unexpected '(', expecting "::" Regarding your comments on the parameters to uvm_config_db.. You notice that I have the second parameter as *core_if.. I was thinking "*" wild character takes care of actual path specification.. Could you please let me know what I am still missing.

Hello, I am a new user to UVM who is trying to convert Vera Test Bench to UVM. I have a simple SV interface as interface core_if ( input core_client_clk , input core_config_clk); bit core_client_reset; bit core_config_reset; . . . . In my top_tb.sv file I am trying to register this interface (to be used in my tb_env) core_if core_intf ( .core_client_clk (core_client_clk), .core_config_clk (core_config_clk) ); uvm_config_db#(virtual vmidmt_if)::set(null, "*core_if", "core_if", core_intf) ; But I get compile error when using the "uvm_config_db" as described above Importing package quvm_addons_pkg ** Error: ../top_tb.sv(94): near "(": syntax error, unexpected '(', expecting "::" PLease advise, I tried to cross check my usage of uvm_config_db.. but could not figure out what I am doing wrong