[Call for Participation - Federated Simulation Standard proposed working group and first meeting]

Accellera is initiating a Proposed Working Group (PWG) to identify industry interest in developing a standardized communication interface to enable interoperability of virtual modeling, simulation, and integration throughout the product lifecycle. The intent of this communication standard is to facilitate the creation of a distributed and orchestrated (“federated”) multi-domain simulation framework, compatible with and complementary to existing approaches used in different industries and sectors.

The first Proposed Working Group meeting will be held over two days in Toulouse, France. On Monday September 25, attendees are invited to present use cases, requirements, and expectations of the standard. Tuesday September 26 will focus on the organizational aspects and intended alignment with other project initiatives or organizations, such as IRT Saint-Exupery, Eclipse Foundation, Linaro, etc. 

More information how to join the Proposed Working Group and register to attend the first meeting on September 25+26 can be found here:

https://accellera.org/activities/proposed-working-groups

 

[Templated UVM-SC TB generation using Easier-UVM]

I suggest to contact the presenters/authors listed at the first page of the presentation.

[Error: (E521) immediate notification is not allowed during update phase or elaboration phase]

The UVM-Connect library is not under definition/development at Accellera. Please contact the organization where you found the download of this library for support.

[Oscillator modeling with SystemC-AMS]

sca_lsf::sca_add    sub1("sub1");

Due to this, your feedback is not negative. Either change the gain to -2.5 or replace sca_lsf::sca_add by sca_lsf::sca_sub.

BTW, it is not a good coding practice to instantiate an adder and call it sub1... (difficult to debug)

After this change, it should work

[Synthesize SystemC code in Vitis HLS 2022.1]

be aware of this

https://support.xilinx.com/s/article/73613?language=en_US

 

[Is there a forum where the ucis xml coverage report is discussed?]

You can post your FC4SC questions in the SystemC Verification forum:

https://forums.accellera.org/forum/38-systemc-verification-uvm-systemc-scv/

[Verilog AMS netlist needs to be wrapped by a verilog AMS file.]

This forum discusses SystemC-AMS, not Verilog-AMS. Please contact your EDA tool provider to answer your Verilog-AMS specific questions.

[SystemC Community Portal LIVE]

Hello SystemC enthusiasts,

At the SystemC Evolution Day we announced the renewed domain and website systemc.org. The website sources are hosted on GitHub, so we appreciate pull requests from the SystemC community to contribute content! More information how to contribute can be found here.

[Connecting AMS and TLM through discrete-event]

Quote

Is there anything that needs attention when interconnecting TLM and AMS models?

Your approach to connect he SystemC/TLM world with the SystemC-AMS is correct: to cross the discrete-event / TDF MoC boundary, dedicated converter ports are available for this, called sca_tdf::sca_de::sca_in/out, as explained in section 2.4 of the SystemC-AMS user's guide.

Special attention is required to understand when digital discrete-event samples are (made) available in the TDF context. In the case of fixed TDF timesteps, a signal change at an input port of type sca_tdf::sca_de::sca_in is not immediately picked-up by the TDF model, since it runs on its own time step (set by set_timestep), which means the value will be used at the next TDF time step. In case you expect immediate action in the TDF model, then you need to make use of the dynamic timestep feature in SystemC-AMS, by using the SystemC-AMS TDF method request_next_activation in a change_attributes callback. This is explained in section 2.4.3.

Note that when using dynamic timestep in a TDF module, you need to make sure other TDF modules in the same TDF cluster support dynamic timesteps, as explained in section 2.1.2. This means all other connected modules should "opt-in" to indicate that they support dynamic timesteps by explicitly calling the method accept_attribute_changes.

[(max. 20 printed)]

It is recommended not to use VCD trace files for TDF, LSF and ELN signals due to their continuous-time nature. Instead you should use the tabular tracefile format. You can open that it many tools since it is basically a ASCII based file with space-separated columns.

[(max. 20 printed)]

You need to specify the timestep to at least one TDF module or TDF port, using method set_timestep. In a TDF module this method should be called in the callback set_attributes. See section 2.3.1 (Discrete-time modeling) and Example 2.11 in the SystemC-AMS User's Guide.

 

[Want to explore statistics_config class]

statistics_config is not part of the SystemC AMS language standard (IEEE 1666.1-2016) and as such also not described in the users guide.

[need help :( : Error: (E109) complete binding failed: 4 binds exceeds maximum of 1 allowed: port 'adc_sub_1.sca_tdf_in_0' (sca_tdf::sca_in) In file: ../../../../source/src/sysc/communication/sc_port.cpp:231]

code not compete (ADC missing).

[Question about the input converter port of TDF block]

The behavior your describe is correct and caused by the discrete-event behavior of the SystemC kernel. I suggest to read section 2.4.1 (Reading from the discrete-event domain) in the SystemC AMS user guide.

 

[Question about sca_de_rswitch]

There is no such thing as a default state. Equation 7.34 in the 1666.1-2016 LRM defines the contribution of the switch to the equation system, and depends on the value of the control signal (ctrl) of the switch. Since the type of the control signal should be a Boolean value, the initial value can be true or false, which is driven from the digital discrete-event side.

[Can we use systemC for power modelling of hardware]

Yes, many publications have been posted on this during the last decade. Check IEEEEXplore for the papers. Another approach is check publications from DOCEA POWER, a company which was focusing on this, and is still active in this domain (although under a different name)

[SystemC AMS application examples now available]

Accellera released the SystemC AMS user's guide application examples, which are available for download via this link.

These examples can be executed using your preferred EDA tools, as long as they support the SystemC and SystemC AMS language standard. Alternatively, you can use the open source SystemC and SystemC AMS reference implementations. Instructions for installation and execution can be found in the INSTALL or README files as part of these packages.

We welcome your feedback!

[Tracing ELN Nodes (Voltages and Current)]

The SystemC AMS standard defines in section 9.1.2.6 (sca_util::sca_trace) that it can trace objects of type sca_traceable_object. Since all ELN primitives are derived of this type, you can simply trace the ELN component itself, see example below
 

SC_MODULE(eln_circuit)
{ 
  // node declaration
  sca_eln::sca_node n1;      // ELN node
  sca_eln::sca_node_ref gnd; // ELN ground

  // component declaration
  sca_eln::sca_vsource vin;
  sca_eln::sca_r       r1;

  // constructor including ELN netlist
  eln_circuit( sc_core::sc_module_name nm )
  : vin("vin", 0.0, 1.23), 
    r1("r1", 1e3)
  {
    // Only ELN primitives requires explicit timestep assignment to one element
    vin.set_timestep(1.0, sc_core::SC_MS);
 
    // netlist
    vin.p(n1);
    vin.n(gnd);
 
    r1.p(n1);
    r1.n(gnd);
  }
};


int sc_main(int argc, char* argv[])
{
  eln_circuit cir("eln_circuit");
  
  sca_util::sca_trace_file* tf = sca_util::sca_create_tabular_trace_file("trace.dat");
  sca_util::sca_trace(tf, cir.n1, "v_n1");
  sca_util::sca_trace(tf, cir.vin, "i_through_vin");
  sca_util::sca_trace(tf, cir.r1, "i_through_r1");

  sc_core::sc_start(1.0, sc_core::SC_MS);

  sca_util::sca_close_tabular_trace_file(tf);

  return 0;
}

 

[SystemC-AMS learning resources/examples]

The 2020 edition of the SystemC AMS user's guide is available here

https://www.accellera.org/downloads/standards/systemc

[SystemC AMS User's Guide 2020 edition now available]

The Accellera SystemC AMS Working Group released the 2020 edition of the SystemC AMS User's Guide. You will find the user's guide on this page:

https://www.accellera.org/downloads/standards/systemc

This version of the user's guide is fully compatible with the SystemC AMS standard released as IEEE Std. 1666.1-2016. It describes all the features introduced in the SystemC AMS language standard during the last decade. For example, the user’s guide now explains the use of the dynamic timed data flow capabilities, to make AMS system simulations even more efficient and running even faster.

The SystemC AMS Working Group is currently preparing the release of the user's guide application examples as separate download. Availability of these application examples will be communicated at a later stage.

Please use this forum to post your questions or remarks on the user's guide.

[can we input a stimuli from a text file ?]

The code snippet listed above shows that the file is repeatedly opened in the processing() method, since this method is called at each time step. Instead, the file should only be opened once, e.g. in the module constructor or initialize() callback. Note that in this case you need to make the variable of type ifstream a (private) member of the class, so other methods can access this variable.

[SystemC-AMS learning resources/examples]

Indeed, the Accellera SystemC AMS working group is currently active in updating the SystemC AMS user's guide, including an detailed explanation of the dynamic TDF features introduced since SystemC AMS 2.0 (and also incorporated in the IEEE 1666.1 standard) and obviously removing deprecated methods.

Examples have been presented in various workshops and tutorials given the last decade at DATE, DVCon Europe, DAC conferences. Please check the SystemC AMS community pages for some of the links.

https://accellera.org/community/systemc/about-systemc-ams

The "golden reference" for SystemC AMS documentation is actually the IEEE 1666.1 standard itself. Although it might require some practice to understand all the formal definitins and terms, it well explains the underlying concept and the modeling capabilities of the language. The standard can be found here, and thanks to Accellera you can download a copy via the IEEE Get Program here:

https://standards.ieee.org/standard/1666_1-2016.html

It is well known that SystemC AMS is much faster than Simulink. Actually I consider your 20x speed improvement rather modest, probably since your design is relatively small (this also holds for most of the academic papers I've seen). My observation is that bigger systems in SystemC-AMS show an even bigger speed difference in favor of SystemC-AMS.

[Set timestep in ELN module]

The (old) SystemC AMS User's Guide is now directly accessible via this link:

http://www.accellera.org/images/downloads/standards/systemc/OSCI_SystemC_AMS_Users_Guide.pdf

And also listed in the overview of SystemC standards:

http://www.accellera.org/downloads/standards/systemc

As mentioned before, the AMS Working Group members are currently working on the update of the User's Guide by including the dynamic TDF timestep features which are also part of the IEEE 1666.1 standard.

[Set timestep in ELN module]

Please note that the electrical primitives are predefined elements using the ELN model of computation; there is no mechanism to create your own electrical primitives. As such there is no such thing as a SCA_ELN_MODULE. Primitive modules can only be created for the TDF MoC, hence the SCA_TDF_MODULE macro as alternative to the class sca_tdf::sca_module.

Wrt the the SystemC AMS 1.0 User's Guide, I will start an action to make it available independently of the LRM.

Although the authors of the User's Guide are quite busy with other things, they full recognize the need to update the guide including the Dynamic TDF features as introduced in AMS 2.0 and IEEE1666.1. We hope to announce an update of the document in the coming period.

[Error: System not scheduable]

It looks like you have a multi-rate system, i.e. somewhere you defined a <port>.set_rate(..) in a set_attributes callback. Now you try to access the n-th sample at this port, like <port>.read(<sample>), but the nth sample is higher than the rate specified. This means you have either the wrong rate, or reading a sample outside the range defined by the rate.