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  1. How do you disable a particular register or field in a register from being bit bashed? I tried this example but it doesn't work: uvm_reg_bit_bash_seq reg_bitbash ; reg_bitbash = reg_bit_bash_seq::type_id::create("reg_bitbash", this); reg_bitbash.model = m_env.model.eq;//set the register model for the seq //I'm trying to disabe MY_REGISTER below with "NO_REG_BIT_BASH_TEST", but though it compiles and simulates, it doesn't remove MY_REGISTER from the bit bash. uvm_resource_db#(bit)::set({"*", m_env.model.eq.MY_REGISTER.get_full_name(),".*"}, "NO_REG_BIT_BASH_TEST",1,this); re
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