caprice24

How do you disable a particular register or field in a register from being bit bashed? I tried this example but it doesn't work: uvm_reg_bit_bash_seq reg_bitbash ; reg_bitbash = reg_bit_bash_seq::type_id::create("reg_bitbash", this); reg_bitbash.model = m_env.model.eq;//set the register model for the seq //I'm trying to disabe MY_REGISTER below with "NO_REG_BIT_BASH_TEST", but though it compiles and simulates, it doesn't remove MY_REGISTER from the bit bash. uvm_resource_db#(bit)::set({"*", m_env.model.eq.MY_REGISTER.get_full_name(),".*"}, "NO_REG_BIT_BASH_TEST",1,this); reg_bitbash.model.reset(); reg_bitbash.start(m_env.crb_m_agent.m_sequencer); reg_bitbash.model = m_env.model.eq;//set the register model for the seq //doesn't work below, though it compiles and simulates uvm_resource_db#(bit)::set({"*", m_env.model.eq.MY_REGISTER.get_full_name(),".*"}, "NO_REG_BIT_BASH_TEST",1,this); reg_bitbash.model.reset(); reg_bitbash.start(m_env.crb_m_agent.m_sequencer); After this, the simulation runs and does the bitbashing of all the registers, and includes the register that I don't want to be bitbashed.