I am new to RAL and I am running the default uvm_reg_hw_reset_seq in my test. The test is failing for a register with non zero reset value. It is passing for others which have 0 as the reset value. I get an error as follows :
"m_ral_model.xxxx_REG" value read from DUT (0x0000000000000035) does not match mirrored value (0x00000000xxxx0000).
The mirrored value shows 0 instead of 'h35
I can see the read transaction on the bus, i.e. 'h35 being read on the bus but somehow I get the above error. Also in the generated ral model I can see the configured value for this register is correct ('h35)
I am also running uvm_reg_bit_bash_seq and uvm_reg_access_seq sequence which are passing and I can see the transactions on the bus.
What could be the possible reasons for this kind of mismatch only in case of reset seq ?
