If an IP should be designed with a parameterized interface and additional ports, which should use the same parameter, then this cannot be directly handled in SystemVerilog.
So, obviously, you cannot write something like
interface bus #(N = 8) ();
logic [N-1:0] adr;
modport send (
output adr);
endinterface
module m
(bus.send intf0,
input adr_pure1 [intf0.N-1:0]);
endmodule
So, the parameter has to provided twice. Unfortunately, it is even not possible to do a check at elaboration time that the values are identical.
interface bus #(N = 8) ();
logic [N-1:0] adr;
modport send (
output adr);
endinterface
module m
#(M = 8)
(bus.send intf0,
input adr_pure1 [M-1:0]);
if (M != intf0.N) $error("unequal parameters");
endmodule
Hierarchical names cannot be used in constant expression. Is there a good reason for this limitation?
Best regards,
Thomas