aynsley

Doulos will be running a lunchtime workshop entitled Easier UVM - Functional Verification for Mainstream Designers on Wednesday June 8th at DAC, San Diego. For full details, see http://www.doulos.com/content/events/easierUVM.php John A

The UVM Golden Reference Guide shares the same format as the 7 other GRG titles Doulos currently publish. Unlike the Accellera reference guide, the GRG does not attempt to itemize every single feature of UVM (only 95% of them ;-). Nor is it a text book or tutorial. Rather, it provides quick reference information and examples weighted toward the most frequently used topics, along with hints on best practice and pitfalls. We are not planning an e-paper release in the near future, though like the OVM and VMM GRGs, an electronic version may follow in due course.

Doulos will be releasing the UVM Golden Reference Guide at DAC in June 2011. You can find details of the UVM GRG release, plus an introductory video on UVM and a recording of the presentation Easier UVM for Functional Verification for Mainstream Users at http://www.doulos.com/knowhow/sysverilog/uvm/ John A

The delay argument to nb_transport_fw/bw is declared as an input, whereas the delay argument to b_transport is not an input, and is thus in effect a non-const reference. In SystemC TLM-2.0 the delay arguments to each of these calls are non-const, and are intended to be used in the same way for temporal decoupling with both blocking- and non-blocking transport. The UVM implementation is in effect creating a difference in the timing annotation mechanism between the blocking- and non-blocking cases, which is not justified by the TLM-2.0 standard. So I guess that - either this was not intentional, and should be fixed - or was intentional, and should be documented accordingly - or nobody cares and we should leave well alone

New article "Easier UVM - for VHDL and Verilog Users" posted on http://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm/. In this article we take a look at UVM by considering how you would use UVM to represent ideas familiar to the Verilog or VHDL users, ideas such as design entities, modules, processes, ports, parameters, generics and configuration. Rather than trying trying to demonstrate all the fancy features of UVM, we will deliberately restrict ourselves to a small, well-behaved subset of the UVM library.

Doulos announces the release of the UVM Adopter Class, a full-scope 4-day training course teaching constrained random coverage-driven verification using UVM, which is available for immediate delivery on your site, worldwide. The UVM Adopter Class is part of Doulos' portfolio of hardware, verification, and ESL training classes, which now includes a full range of embedded software training classes. See http://www.doulos.com/content/news.php