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shubham_v

system c,tlm & system verilog interfaces

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Hi ,

I was having doubt over using these interfaces defined in diff languages.

I am comparing 3 of the inerfaces below as follows:

  1. SYSTEM VERILOG - In system verilog as much as i am aware about,we will be declaring a common interface and give the direction for inputs & outputs via modports and driving the blocks with a common clock.
  2. SYSTEM C -In system c, we will be inheriting interface from sc_interface,declaring the type of operation required ,that is in turn defined in the required type of channel and then executed.
  3. TLM- There are diffrent type of predefined interfaces,which will be used depending on our requirement  such as b_transport for LT MODEL,and nb_transport for AT MODEL.

My question is, in interfaces we are defining the inputs and ouputs in sys.verilog and connecting them.Then what about in system c and tlm ?

Is there any possibility of declaring the inputs in system c and tlm interfaces? What i think is ,as these are already predefined ,so we dont need to alter anything over there in the interfaces.

And even if we got to change any thing in the interfaces,complexity might increase ?

This is the confusion which i am getting when working with them,please let me know how exactly are they differeing during defining the inputs and outputs .

 

Thanks in advance.

Regards,

Shubham 

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The term 'interface' (and for that matter 'virtual') is used in somewhat different ways in SystemVerilog than in SystemC. TLM is simply and library built on SystemC that has some well understood standard SystemC interfaces.

Fundamentally, the concept of direction as used in hardware (and hence Verilog) does not translate to SystemC particularly well. In fact, it is somewhat annoying that we have the sc_in<T>, sc_out<T> ports in SystemC because it confuses most folks. It is best in SystemC to think like a C++ programmer. The way that SystemC views "input" and "output" is by observing data flow semantics of function calls. If I have a function with the signature put(int value), then I expect I am moving data from the caller to the callee.

SystemC views the concept of interface in the same manner as other object oriented (OO) programming languages do. An OO interface class is simply an abstract class that exclusively contains pure virtual methods. SystemVerilog as of 2012 also has this concept in the manner of 'interace class', but this was added later.

Thus SystemVerilog uses the keyword 'interface' in three completely different manners:

  • interface blocks provide a wrapper around signals as a method of bundling signals hence the syntax:
  • interface Bus( input clock );
      logic[7:0] address, data;
      logic rw;
      modport cpu_mp( output address, rw, inout data );
      modport mem_mp( input address, rw, inout data );
      clocking cb @(posedge clock);
        input address, data, rw;
      endclocking
      modport verif_if;
    endinterface

    Note: semantically an interface is somewhat of a super module because it may contain initial, always, assign and hierarchy.

  • SystemVerilog's virtual interface is simply references to instances of interface blocks to be used inside classes.

  • SystemVerilog interface classes are more like C++

  • interface class Print_if;
      pure virtual function void print( string message );
    endclass
    
    class A implements Print_if;
      function void print( string message );
        $info("%s", message );
      endfunction
    endclass

     

By contrast C++ would use:

class Print_if
{
  virtual void print( std::string message ) = 0;
};

class A
: Print_if
{
  void print( std::string message )
  {
    std::cout << message << std::endl;
  }
};

 

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