using sc_vector to Pass an Array between Modules

[wasim6691]

Hi 

I have to use the sc_vector command to pass an array let's say  Array[16][16]  between the modules. Kindly can you tell me how to write the input side vector at the MODULE A and output side vector at the MODULE B to pass this array. I am beginner and donot know how to use the sc_vector command. Thanks

[David Black]

sc_vector was designed for use during elaboration. sc_vector semantics are based on std::vector. For that matter, why are you not using std::vector? Are you passing an elaboration call. Furthermore, you would simply pass variables by reference in C++ anyhow. For a 2-dimensional array you would simply use a vector of vectors. Your basic problem sounds like a severe lack of C++ basics.

[wasim6691]

Hi David,

I have to define 16 ports of sc_vector<sc_out<sc_uint<4>>>    some-vector ;    and pass the array elements in parallel through those 16 ports between the Modules. std::vector I do know but for my case I have to dedicate 16 ports at the MODULE A and 16 ports at the MODULE B to make the access of array elements in parallel. i am defining my vector as described in bold but need help how to pass array. Thanks

[maehne]

If you insist to instantiate 16 separate ports to transfer each array element separately from each other, you will also have to write/read the elements in your code one after another using, e.g., a loop over the array. From a simulation point of view, all writes will happen at the same time.

[wasim6691]

Hi Maehne

I want to pass 16 vectors over these 16 ports.  Let's say  each vector A1[9], A2[9]............ A16[9] on each of these 16 ports. thanks. For one array value,  i can use x.write() or x.read commands. but I want to pass vectors on each of the ports. I can use pointers but If there is any other way to pass vectors through ports that would be so nice of you to guide me. thanks

[maehne]

Then, you have to express the vectors as an appropriate data type, which fulfils the conditions for the template parameter T of the port/bound signal (cf. to clause 6.4.3 of IEEE Std 1666-2011), i.e., the data type needs to implement the equality operator==, stream operator<<, and assignment operator= as well as a default constructor. E.g., you could try to use a suitable data type from the Eigen library.