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hugemx830202

Unsuccessful on uvm_config_db#(int)::set(this, "tb_env", "en_*", 1)

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I found that I can't mulit config inst as following in UVM1.0

In test case build_phase(), I tried to use uvm_config_db#(int)::set(this, "tb_env", "en_*", 1), but failed, could you helps?

I original defined en_1, en_2, en_3 in tb_env, and register to the factory by `uvm_field_int(en_1, UVM_ALL_ON), `uvm_field_int(en_2, UVM_ALL_ON), `uvm_field_int(en_3, UVM_ALL_ON)

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You are not providing enough code to replicate your situation. The config DB depends on the object hierarchy as well as the types of the configuration item.

One possible problem is that the field automation macros use uvm_bitstream_t for all non-string and non-object types. Try:

uvm_config_db#(uvm_bitstream_t)::set(this, "tb_env", "en_*", 1)

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The config DB depends on the object hierarchy as well as the types of the configuration item.

The config_db::set call is going to set the value for "test.tb_env.en_*" (assuming the name of your test is "test") since it creates the name from {this.get_full_name(),".","tb_env",".","en_*"}.

One possible problem is that the field automation macros use uvm_bitstream_t for all non-string and non-object types. Try:

uvm_config_db#(uvm_bitstream_t)::set(this, "tb_env", "en_*", 1)

Janick is correct that the types have to match. However, for the uvm_field_int macro usage, the code checks for both types on the hidden get() call. Most likely, your problem is with the path. Does it work if you do

uvm_config_db#(int)::set(this, "tb_env", "en_1", 1)

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Hi,

There are some parts of my codes, seems uvm_config_db#(uvm_bitstream_t)::set(this, "TB_env_inst", "test*", 1) can not update test/test1/test2 values in TB_env, are there some thing wrong with my code? I just tried to use uvm_config_db#(uvm_bitstream_t)::set(this, "TB_env_inst", "test1", 1), it works well, so I think my path is correct, could you help? Does UVM1.0 still support multi config or is that a potential bug in UVM1.0?

1. in TB env:

class TB_env extends uvm_env;

int test = 0;

int test1 = 0;

int test2 = 0;

`uvm_component_utils_begin(tb_axi_ovc_self_loop)

`uvm_field_int (test, UVM_ALL_ON)

`uvm_field_int (test1, UVM_ALL_ON)

`uvm_field_int (test2, UVM_ALL_ON)

`uvm_component_utils_end

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

endfunction

endclass

2. in Test case

class testcase extends uvm_test;

TB_env TB_env_inst;

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

uvm_config_db#(uvm_bitstream_t)::set(this, "TB_env_inst", "test*", 1);

//create TB_env_inst

endfunction

endclass

BR

Mike

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class TB_env extends uvm_env;

int test = 0;
int test1 = 0;
int test2 = 0;

`uvm_component_utils_begin(tb_axi_ovc_self_loop)
`uvm_field_int (test, UVM_ALL_ON)
`uvm_field_int (test1, UVM_ALL_ON)
`uvm_field_int (test2, UVM_ALL_ON)
`uvm_component_utils_end

virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
[I][B]
    void'(get_config_int("test", test));
    void'(get_config_int("test1", test1));
    void'(get_config_int("test2", test2));
[/B][/I]
endfunction

endclass

Can anyone tell me why it work after adding these three lines?

I don't think we must add these lines, at least we have not these code in OVM, but OVM code can work.

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