registering sequence with a particular phase of sequencer

[ecpratik]

Hello ,

I have one sequence x_seq which is associated with x_sequencer. Inside UVM , I think we have facility to register a specific sequence with particular phase.

For example : x_seq is reset sequence so it will be associate with reset_phase().

Can anyone explain with example how to register a sequence with a particular phase with the help of uvm_config_db ?

Thanks.

[jwagner]

Hello,

you should add this code in the build phase of yout testcase:

// reset phase sequence

uvm_config_db#(uvm_object_wrapper)::set(this,

"path_to_your_sequencer.reset_phase",

"default_sequence",

your_reset_sequence::type_id::get());

// main phase sequence

uvm_config_db#(uvm_object_wrapper)::set(this,

"path_to_your_sequencer.main_phase",

"default_sequence",

your_main_sequence::type_id::get());

[ecpratik]

Thanks ,

I have tried your example , but its still not calling the sequence from the test.

Following is the sample code which I tried in my test :

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

my_tb = my_testbench::type_id::create("my_tb", this);

uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.reset_phase","default_sequence",my_seq::type_id::get());

endfunction:build_phase

[jwagner]

Hi,

at a first glance, the code seems fine. You probably didn't set the right path to your sequencer, so you sequence is not registred for this phase. Try UVM_FULL as verbosity level to debug, so for each sequencer instance and phase an info will be printed out.

In your case one should look like

[PHASESEQ] Starting default sequence 'my_seq' for phase 'reset'

if the sequence is properly registred, or

[PHASESEQ] No default phase sequence for phase 'reset'

if not. If its registered, you should search the problem in your seqeunce.

[mastrick]

Another possibility is that your sequence path is fine but your reset phase is finishing in 0 time. If this sequence is supposed to complete before reset phase is done, then make sure the sequence raises and drops an objection to the phase. The sequence can get a handle to the current phase via its handle to its parent sequencer.

[ecpratik]

Hi jwanger ,

I tried following sample code to register a sequence in pre_reset phase into build phase of test code and ran with UVM_DEBUG:

uvm_config_db #(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.pre_reset_phase","default_sequence",my_seq::type_id::get());

But it gave me following message :

[PHASESEQ] No default phase sequence for phase 'pre_reset'

Which means that it did not register the my_seq with pre_reset phase. I cross checked my sequencer path and it is proper.

Do we have any working example in which registering sequence to a particular phase is working?

[ecpratik]

Here is flow to register a sequence with uvm phase along with proper raise and drop objection mechanism inside sequence which is working and running properly :

Inside Test’s build phase , registering the sequence with particular UVM phase with help of uvm_config_db :

=======================================================================================

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.pre_reset_phase","default_sequence",my_powergood_seq::type_id::get());

uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.reset_phase","default_sequence",my_reset_seq::type_id::get());

uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.configure_phase","default_sequence",my_cfg_seq::type_id::get());

uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.main_phase","default_sequence",my_test_seq::type_id::get());

uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.shutdown_phase","default_sequence",my_flush_seq::type_id::get());

Inside Base Sequence’s pre_body() and post_body() tasks for raise and drop objection mechanism :

=======================================================================================

virtual task pre_body();

if (starting_phase!=null) begin

`uvm_info(get_type_name(),

$sformatf("%s pre_body() raising %s objection",

get_sequence_path(),

starting_phase.get_name()), UVM_MEDIUM);

starting_phase.raise_objection(this);

end

endtask

// Drop the objection in the post_body so the objection is removed when

// the root sequence is complete.

virtual task post_body();

if (starting_phase!=null) begin

`uvm_info(get_type_name(),

$sformatf("%s post_body() dropping %s objection",

get_sequence_path(),

starting_phase.get_name()), UVM_MEDIUM);

starting_phase.drop_objection(this);

end

endtask

Edited January 7, 2013 by ecpratik