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Integrating uvm vip in verilog environment

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I have created a verilog wrapper over UVM VIP. I want to integrate it in DUT's environment which is in verilog. I have created a model of verilog top testbench for my VIP testing, but in place of verilog DUT I am using a verilog wrapper containing my VIP with some components disabled. So, in the verilog top tesbench, I have instantiated two verilog wrappers -

- one having UVM VIP with master and monitor enabled (to be used as VIP)

- and the other also having UVM VIP but only slave enabled (to be used as DUT)

Now, how to use the tests of VIP and synchronize UVM phases for the components inside both wrappers or how can I make a common UVM or verilog test so that phases of all components get synchronized.


Edited by Mahak
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Better way would be to use different environment classes and instantiate the environment top extended from uvm_top based on the test that you want to run.

1) uvm_vip_env (back to back UVM vips) connected and use them in the uvm_test classes

2) uvm_dut_env (UVM vip instantiated to be connected with DUT) and then use that with the uvm_test classes.

You are actually defeating the purpose of UVM plug-n-play by creating verilog over uvm vips and then instantiating them conventionally.



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