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UVM Reg Model Register Read Write

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I would like to write a register with a random value and read back and again I want to write back the same register with '0'.

the problem I'm facing is - I could not able to write '0' . AXI Slave write transaction is not all happening for write '0' while reg model is getting updated with '0' . So seeing register mismatch errors. Could you please tell me why write transaction is not happening if I write '0' . Write back is happening if I write other values other than '0'.

Snippet of the code:

data[31:0] = 32'hFFFF_FFFF;



compare_model_dut_reg(model1.REG_A); //task to compare dut with reg model ( read_reg)

data[31:0] = 32'h0000_0000;// WRITE '0' is not happening .



Model is getting updated with value'0' but It is not happening at DUT side. Item is not getting generated for write '0' itself.

Please throw some light on this. Thanks

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