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Synopsys Webinar: How to Simplify Testbench Debug and Improve Turnaround Time

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By popular demand the UVM Debug Webinar has been recorded and uploaded for you to watch.
Your local SNPS-AC can provide you with the associated FAQ that came out of the live webinar session.

Deploying UVM Effectively link on the Webinar page:

What is it about:
The number of companies using SystemVerilog testbench with UVM or migrating to UVM has increased dramatically. They are moving to SystemVerilog because coverage, assertions and object-oriented programming concepts like inheritance and polymorphism allow them to reuse code much more efficiently so they can find not only the bugs they expect, but also corner-case issues. They have proven that building testing frameworks that randomly exercise the stimulus state space of a design-under-test and analyze completion through coverage metrics is the most effective way to validate a large chip. UVM offers a standard method for abstraction, automation, encapsulation, and coding practice, allowing teams to build effective, reusable testbenches quickly that can be leveraged throughout their organizations.

For all of its value, UVM deployment has unique challenges, particularly in the realm of debugging. Some of these issues are:

- Phase management: objections and synchronization
- Thread debugging
- Tracing issues through automatically generated code, macro expansion, and parameterized classes
- Default error messages that are verbose but often imprecise
- Extended classes with methods that have implicit (and maybe unexpected) behavior
- Object IDs that are distinct from object handles
- Visualization of dynamic types and ephemeral classes

Debugging even simple issues can be an arduous task without UVM-aware tools. This public webinar will review how to utilize VCS and DVE to most effectively deploy, debug and optimize UVM testbenches.


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