budisantoso Posted July 17, 2012 Report Share Posted July 17, 2012 Hi, I run into problem when dealing with UVM phasing. I have 2 components that i want to synchronize: test and driver. In each component, i implement task::main_phase. In the main_phase implementation at test, i put raise and drop objection to make sure that the test will finish properly. task main_phase(uvm_phase phase); phase.raise_objection(this); sequence.start(sequencer); phase.drop_objection(this); endtask In the main_phase implementation at driver, i do not put raise and drop objection since it is free running component (forever loop). task main_phase(uvm_phase phase); send_frame(xactn); endtask However, when i run the test, the simulation will stop prematurely where the send_frame function has not finished yet. It seems that the drop_objection at the test is being done before the send_frame finish. From what I understand, the main_phase is exercised bottom up where main_phase at the driver will be executed first before main_phase at the test. Anyone can help me on this? How can i debug such a phasing problem? Thank You, Budi Quote Link to comment Share on other sites More sharing options...
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