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UVM Phase sequence

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I run into problem when dealing with UVM phasing.

I have 2 components that i want to synchronize: test and driver.

In each component, i implement task::main_phase.

In the main_phase implementation at test, i put raise and drop objection to make sure that the test will finish properly.

 task main_phase(uvm_phase phase);

In the main_phase implementation at driver, i do not put raise and drop objection since it is free running component (forever loop).

 task main_phase(uvm_phase phase);

However, when i run the test, the simulation will stop prematurely where the send_frame function has not finished yet. It seems that the drop_objection at the test is being done before the send_frame finish.

From what I understand, the main_phase is exercised bottom up where main_phase at the driver will be executed first before main_phase at the test.

Anyone can help me on this? How can i debug such a phasing problem?

Thank You,


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There is no defined ordering of the execution of main_phase between components. They could be called in any order, and they will be terminated when there are no outstanding objections to the phase.

You may be able to make your existing code work by having the driver affect when the sequence completes. If the driver does not call item_done() until it has finished send_frame(), then the sequence could not finish (and the objection could not drop) until send_frame() ends.

In fact, it would be more standard to start your driver in the run_phase(), conditioned by reset, so that it is just waiting for the sequence to come alive in the main phase. If you do your driver this way, it will not be terminated by the end of main_phase at all, but you will still need to extend a phase after main so that the end of simulation does not occur in 0 time.

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