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SEQ_NOT_DONE Error during run time

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Hello Folks,

I am new to UVM and trying to contruct a simple testbench with user defined sequences and sequence libraries.

In my sample testcase's build_phase I have

function void build_phase(uvm_phase phase) ;

vmidmt_client_seq_base seq_lib ;

seq_lib = vmidmt_client_seq_base::type_id::create("seq_lib", this) ;

uvm_config_seq::set(this, "*","default_sequence", seq_lib) ;

uvm_config_int::set(this, "*","min_random_count", 100) ;

uvm_config_int::set(this, "*","man_random_count", 100) ;

super.build_phase(phase) ;

uvm_report_info(get_name()," vmidmt_test_seq_lib build phase complete") ;

endfunction : build_phase

Here vmidmt_client_seq_base is simple user defined sequence with run_phase as

task vmidmt_client_seq_base::body() ;


endtask : body

In the run_phase of the testcase I have simple raise and drop objections as below

task vmidmt_test_seq_lib::run_phase(uvm_phase phase) ;

super.run_phase(phase) ;


uvm_report_info(get_name(), "Raising objection") ;

phase.raise_objection(this) ;


uvm_report_info(get_name(), "Dropping objection") ;

phase.drop_objection(this) ;

uvm_report_info(get_name(), "Test should be done whenever stimulus finishes") ;

endtask : run_phase

I get the below error when I run the testcase (run time error)

# UVM_FATAL @ 0: uvm_test_top.tb.vmidmt_client_master.seq@@seq_lib [sEQ_NOT_DONE] Sequence uvm_test_top.tb.vmidmt_client_master.seq.seq_lib already started

Any debug tips or suggestions on what I might be doing wrong is really appreciated.

What does the SEQ_NOT_DONE error actually mean?



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you should first choose the sequence and only then create the sequence. So try to do all the uvm_config stuff prior to any create call.

as far as I remember the uvm_config_seq or _int will be deprecated, so you should use uvm_config_db instead of them.

and finally, I would move the raise_objection and drop_objection to the pre_body and post_body of the sequences.

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you should first choose the sequence and only then create the sequence. So try to do all the uvm_config stuff prior to any create call.s.

Here I am trying to first create the user defined sequence "seq_lib" assign it to default sequence and then my call super.build_phase(phase) creates the tb/sequencer etc.. I did this after reading in some UVM book.. Are you saying this is not the correct procedure? It would be helpful if you elaborate on your above comment.

In the user defined "seq_lib" I do have raise and drop objections defined in the pre_body and post_body. In the testcase itself I have one more objections defined in run_phase (not sure if I need this)

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I can't tell you for sure what works and what doesn't, I learned that you should modify the variables inside a class before you call the create function because the variables may have effect in functions inside the class.

The uvm structure is that you have a top class uvm_test which instantiates the testbench environment. You should select the sequence for this testbench environment and then call the create function.

so, inside the test class this structure should be used:

dut_uvm_tb dut_tb;

virtual function void build();

super.build() ;

uvm_config_db#(uvm_object_wrapper)::set(this, "*dut_tb.dut_env.agent.sequencer.run_phase", "default_sequence", ::specific_sequence::type_id::get());

dut_tb = dut_uvm_tb::type_id::create("dut_tb", this);

endfunction : build

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