chili-chips Posted July 17 Report Share Posted July 17 We are looking for your expert opinion on an interesting question that pertains to Verilog language and simulation results from gtaylormb module calc_envelope_shift import opl3_pkg::*; ( input wire clk, input wire [REG_BLOCK_WIDTH-1:0] block ); logic [REG_BLOCK_WIDTH:0] block_shifted; always_comb block_shifted = block << 1; REG_BLOCK_WIDTH=3, block=3'b111, block_shifted gets 4'b1110. Waveform from Questa: There are no synthesis warnings and no other tools complain because the original syntax is correct. This type of shift is all over the code and proven in both Xilinx and Altera FPGAs. ----------------- The counter-claim is that block_shifted should have gotten 4'b0110, and that Verilator Lint warning is correct: %Warning-WIDTHEXPAND: modules/operator/src/calc_envelope_shift.sv:119:31: Operator SHIFTL expects 4 bits on the LHS, but LHS's VARREF 'block' generates 3 bits. : ... note: In instance 'opl3.channels.control_operators.operator.envelope_generator.calc_envelope_shift' 119 | block_shifted = block << 1; ----------------- As the discussion on this topic is still developing, you can check this link for additional details Quote Link to comment Share on other sites More sharing options...
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