MarcelCostel Posted March 25 Report Share Posted March 25 Hi, i can't wrap my head around this problem. The program keeps looping and won't advance to the next step. I'm making a D-Latch using NAND Gates and NOT Gates, a Generator to serve as clock and input source and a Supervisor to display the data. I'm attaching a link to my code with everything there and the schema below: https://www.edaplayground.com/x/R6k7 Thank you in advance! Quote Link to comment Share on other sites More sharing options...
AmeyaVS Posted March 26 Report Share Posted March 26 Hello @MarcelCostel, What you are trying to achieve here has meta-stable states in the final NAND logic gates. Can you try you simulation with varying initial states in the generator module for signal D and the clk? On another note I would not recommend using SystemC for modelling at gate level simulation. Regards, Ameya Vikram Singh Quote Link to comment Share on other sites More sharing options...
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