Performance and power analyze for architecture exploration

[red_dandelion]

I know SystemC can do system level model for architecture exploration, But how can I adjust the architecture to prove the current one is Ok now! is it dependent on performance or power analysis ?  If so, how can I do performance and power analyze?

[Eyck]

This is a fairly complex topic. I try to summarize in a few sentences

At first you need to define what your requirements are. Let's assume you have a piece of software which needs to run at a certain speed. So the most important factors to this is the perfomance of the processor in terms of instruction per cycle and the performance of the interconnect and memory subsystem in terms of bandwidth and latency. In the next step you need to gather or develop respective models running in cycle-approximate (CA) or cycle-accurate (CT) mode. They need to provide means to collect the timing information like signal and transaction traces. Then you setup test runs and collect the information. In a postprocessing step you can then calculate the relevant measures and check them against your requirements. Now you can reconfigure your elements until the measures fulfill the requirements.

Important here is that you need CA or CT models for the interconnect(s) and the processors. If using TLM2.0 based AMBA interfaces, you might have a look at https://github.com/Arteris-IP/tlm2-interfaces which is also integrated into https://github.com/Minres/SystemC-Components which provides a few more AT protocol implementations on top.