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regarding phase ready to end

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In OVM when the global_stop_request is issued it checks whether any enable_stop_request bit is set, If set it checks stop request task and the phase will be ended accordingly. In stop request task,using set_global_stop_timeout delay is issued

In UVM these features are deprecated and instead phase_ready_to_end and phase_ended are used.

can anyone give a example how these will be worked

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  • 1 month later...

I'm still learning UVM and not familiar with OVM, but it looks like UVM has enable_stop_interrupt bit and a mechanism for an orderly halt of a component's run phase by automatically calling stop(<phase>) if enable_stop_interrupt bit is set. See comments from uvm_component.svh:

// Task: stop_phase


// The stop_phase task is called when this component's <enable_stop_interrupt>

// bit is set and <global_stop_request> is called during a task-based phase,

// e.g., run.


// Before a phase is abruptly ended, e.g., when a test deems the simulation

// complete, some components may need extra time to shut down cleanly. Such

// components may implement stop_phase to finish the currently executing

// transaction, flush the queue, or perform other cleanup. Upon return from

// stop_phase, a component signals it is ready to be stopped.


// The ~stop_phase~ method will not be called if <enable_stop_interrupt> is 0.


// The default implementation is empty, i.e., it will return immediately.


// This method should never be called directly.

extern virtual task stop_phase(uvm_phase phase);



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