Doulos Posted May 25, 2012 Report Share Posted May 25, 2012 (edited) Date: Wednesday June 6 Time: 12.00pm - 1.30pm Venue: Moscone Center, San Francisco (DAC) Room: East Mezzanine Level, Room 220 Doulos CTO John Aynsley will highlight the reasons why you should (or in a few cases should not) be adopting UVM right now, and explain how using SystemVerilog with UVM to create your test benches differs from using Verilog or VHDL. He will explore some of the practicalities of migrating to UVM from other methodologies, discuss using UVM alongside C/SystemC reference models, and introduce register modeling using the UVM register layer. Find out more and register here: http://www.doulos.com/content/events/dac12.php First 50 registrations will receive a copy of the UVM Golden Reference Guide Edited May 28, 2012 by Doulos Quote Link to comment Share on other sites More sharing options...
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