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  1. Date: Wednesday June 6 Time: 12.00pm - 1.30pm Venue: Moscone Center, San Francisco (DAC) Room: East Mezzanine Level, Room 220 Doulos CTO John Aynsley will highlight the reasons why you should (or in a few cases should not) be adopting UVM right now, and explain how using SystemVerilog with UVM to create your test benches differs from using Verilog or VHDL. He will explore some of the practicalities of migrating to UVM from other methodologies, discuss using UVM alongside C/SystemC reference models, and introduce register modeling using the UVM register layer. Find out more and register here: http://www.doulos.com/content/events/dac12.php First 50 registrations will receive a copy of the UVM Golden Reference Guide
  2. The Easier UVM webinar, presented by Doulos CTO, John Aynsley, provides an introduction to the guidelines for learning and using UVM. It is aimed at mainstream designers rather than power users specialising in verification. The webinar comprises two sessions, on successive days, each session being one hour long. It will be broadcast on November 7th and 8th to suit US time zones and again on November 9th and 10th to suit Euro-Asian time zones. View www.doulos.com/EasierUVM for more details and registration links.
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