nVidia's Matchlib

[ManikantaAllam]

Hello seniors, 

I am trying to use NVIDIA'S matchlib's components (cmod & LI Channels) for the first time. 

I'm wondering if I can instantiate & run these directly with systemc & C++ ( Visual Studio - Windows OS) as same as other systemc modules? 

If I can avoid HLS tools' intervention, how can I do this? I am not interested in the synthesis for now.

The reason I am interested in this library is its generic nature and HLS-ability.  For now, I am just interested in writing a simulation framework and using it as part of my other work. 

 

@StuartSwan I hope you could give me some hints regarding this. 

 

 

Thank you & Best regards

Manikanta

[StuartSwan]

Manikanta-

Here are some tips on using Matchlib and the examples:

- I recommend using the fully open-source self-contained kit available here:

https://forums.accellera.org/files/file/126-matchlib-examples-kit-for-accellera-systemc-evolution-day-2020-presentation/

- Follow the README steps in the top level dir.

- You don't need any HLS tools or any other installs to run the examples.

- The kit has been successfully downloaded and run on many flavors of Linux machines.

- It is easiest probably if you use some version of g++ .

- My personal preference if using windows is to use VirtualBox and an Ubuntu Linux virtual machine. If you do this, you can still download Microsoft VSCode from the Ubuntu repositories.

- Some people have reported successfully using this kit on cygwin on Windows, though a few minor changes to the Makefiles may be needed for locations of system libs.

- Microsoft has something similar to cygwin now in the latest windows (linux shell or something like that), so you can try that too.

- The SystemC simulator includes scripts for building with Visual Studio, but the other code in the kit I don't think has been tested with Visual Studio.

Thanks

Stuart Swan

[ManikantaAllam]

@StuartSwan 

Thank you so much for the quickest reply. 

I'll try it out. 

[ManikantaAllam]

@StuartSwan

Hi Swan, 

I am interested in WHVCSource Router, as part of creating a cycle accurate simulation frame work. The router itself is kind of loosely/un-timed implementation as the unrolling and pipelining are left to HLS Tool. Is there a way, which I am missing and must know, that enables system level cycle accurate(approx.) fast simulation without depending on the RTL?

Somewhere, in one of Siemens' webinars, I heard about Back Annotation. Unfortunately, I could not understand it as I am a beginner and could not find any example. 

Is there something you could comment on this?

 

TIA & Best regards

Manikanta 

 

 

 

[StuartSwan]

Manikanta-

The WHVCRouter model in Matchlib is a "wormhole virtual channel" router. It is used in network on chip models.

FYI there is a unit test for the router model in the matchlib dir in in the kit at:

matchlib-main/cmod/unittests/WHVCRouterTop

The model itself is already very close to cycle accurate. Pretty much all of the loops are fully unrolled during HLS, so only

the main loop of the main process remains, and that loop may be pipelined during HLS but the pipeline latency is probably just 1.

So it is basically very close to RTL, it is just in SystemC .

Thanks

Stuart Swan

[ManikantaAllam]

@StuartSwan

Hi Swan, 

Thank you so much for replying.

Yes, I am creating a heterogeneous NoC simulation framework as part of my thesis. I will also modify this router to have different number of virtual channel distribution per ingressport unlike the original one has uniform distribution of no. of virtual channels on all the input ports. 

I have seen and simulated unittests _ WHVC router example already. But also saw all the processes(functions involved in routing) are put in single clocked process. That's where I had the concern regarding the latency mismatch between after HLS and pre HLS simulations. Nevertheless, this level of detailing is sufficient for system level exploration I guess.

I will further see and try to understand it. Thank you again.

 

Best regards

Manikanta