Part selection of ports

[acc_sysC]

Verilog code:

reg [7:0] B;

reg [15:0] ACC;

B[3:0] = ACC[3:0];

Equivalent systemC code:

This module is a stimulus module so I am declaring B as output port

sc_out<sc_bv<8> > B;

sc_bv<8> B_copy;

sc_bv<16> ACC;

B_copy.range(3,0) = ACC.range(3:0);

This is what I want to do but its not possible because range() cannot be used with ports. How should this be done in systemC?

B.range(3,0).write(B_copy);

I also don't want bits 4,5,6,7, to be overwritten with 0s

Please advice

[acc_sysC]

Figured out a way shown below. But is there any other better solution to this?

 

      B_copy = B.read();
      B_copy.range(3,0) = ACC.range(3,0);
      B.write(B_copy);