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TLM wrapper for systemc module

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I have a module that has a bunch of inputs such as a clock(sc_in(bool)), enable(sc_in(bool)), reset(sc_in(bool)) and a vector_in(sc_in(char)) and two outputs: a vector_in(sc_out(char)) and ready(sc_out(bool)).

I want to interface this module with a master that has only one socket using TLM 2.0. I thought of creating a TLM target module that wraps the systemc module  that I have and add functions that will convert generic payload data_ptr  into the systemc_module data(clock,enable signal, reset signal and input vector) and the same for the outputs. Is that the way to do it or there is better method.

Many thanks in advance.


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Actually you are more or less correct. TLM models bus transactions, mostly read and write. These bus transactions would have to be mapped to your vectors. I suppose a bus write sets the sc_in signals and a read samples the sc_out signals. enable would be set upon a write while ready would stall the read until it signals to be done.

clock and reset are independent from the bus transaction so the are not mapped from or to the tlm payload.

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