amedoc Posted July 25, 2022 Report Share Posted July 25, 2022 Hello, I have a module that has a bunch of inputs such as a clock(sc_in(bool)), enable(sc_in(bool)), reset(sc_in(bool)) and a vector_in(sc_in(char)) and two outputs: a vector_in(sc_out(char)) and ready(sc_out(bool)). I want to interface this module with a master that has only one socket using TLM 2.0. I thought of creating a TLM target module that wraps the systemc module that I have and add functions that will convert generic payload data_ptr into the systemc_module data(clock,enable signal, reset signal and input vector) and the same for the outputs. Is that the way to do it or there is better method. Many thanks in advance. Quote Link to comment Share on other sites More sharing options...
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