Jump to content

TLM wrapper for systemc module


Recommended Posts

Hello,

I have a module that has a bunch of inputs such as a clock(sc_in(bool)), enable(sc_in(bool)), reset(sc_in(bool)) and a vector_in(sc_in(char)) and two outputs: a vector_in(sc_out(char)) and ready(sc_out(bool)).

I want to interface this module with a master that has only one socket using TLM 2.0. I thought of creating a TLM target module that wraps the systemc module  that I have and add functions that will convert generic payload data_ptr  into the systemc_module data(clock,enable signal, reset signal and input vector) and the same for the outputs. Is that the way to do it or there is better method.

Many thanks in advance.

 

Link to comment
Share on other sites

Actually you are more or less correct. TLM models bus transactions, mostly read and write. These bus transactions would have to be mapped to your vectors. I suppose a bus write sets the sc_in signals and a read samples the sc_out signals. enable would be set upon a write while ready would stall the read until it signals to be done.

clock and reset are independent from the bus transaction so the are not mapped from or to the tlm payload.

Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...