Phase Domains, Reset Monitors, and Multiple Instances

[ifpk454]

I have a design with multiple instances, each of which can be reset independently and a UVM test bench that will be using the new run time phases.

I would like to synchronize the reset for each instance in the DUT with the corresponding test bench components (scoreboards, monitors, sequencers, etc.)

Currently, we have developed a reset monitor that jumps to the reset_phase for the UVM test bench. I am thinking of creating a reset monitor for each instance that can be reset independently.

Does anyone have an example of how to use the phase domains?

Is this a good approach?

[mastrick]

I would recommend a reset monitor for each instance that informs its clients about reset state some other way than jumping to reset_phase, e.g. an analysis port. The usage recommendation from Accellera is still evolving, but it is generally agreed that testbench objects that are not involved in providing stimulus should not use phasing. The prime reason is that phasing implies a progression of phase states leading to a final state when the run ends, but an IP component could go into reset and stay there for the rest of the sim. Along with your reset monitor, you may want a reset driver. The behavior of this reset driver, being stimulus, could be specified as part of the phasing. For example, you might have a reset_phase sequence that causes the driver to assert reset.

[ifpk454]

That makes sense - thanks.

I would recommend a reset monitor for each instance that informs its clients about reset state some other way than jumping to reset_phase, e.g. an analysis port. The usage recommendation from Accellera is still evolving, but it is generally agreed that testbench objects that are not involved in providing stimulus should not use phasing. The prime reason is that phasing implies a progression of phase states leading to a final state when the run ends, but an IP component could go into reset and stay there for the rest of the sim. Along with your reset monitor, you may want a reset driver. The behavior of this reset driver, being stimulus, could be specified as part of the phasing. For example, you might have a reset_phase sequence that causes the driver to assert reset.