ccherich Posted April 12, 2012 Report Share Posted April 12, 2012 Since uvm_reg models are built out of uvm_objects, and don't do automatic reseeding using uvm_create_random_seed() when they are created, they seem to be very susceptible to changes in the random seeding structure of the testbench. Ie., adding a thread or component can change the seed for the reg model. I am using the reg model as a component of my environment, and randomizing it and calling the update() method to initialize my DUT. So any change in the reg model seeding has a pretty drastic effect on my sim. I can add reseed() calls in the constructors of all of my reg model classes, but that is a pain, especially since they are tool generated in my case. Can anyone comment on why the uvm_reg stuff is built of uvm_objects instead of uvm_components? Anyone have a different workaround for this problem? Thanks in advance, Cory Quote Link to comment Share on other sites More sharing options...
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