error: no match for call to ‘(sc_core::sc_out<unsigned int>) (sc_core::sc_signal<sc_dt::sc_uint<32> >&)’ top->y(y);

[Abdul Razak H S]

Design in verilog

module add(clk,a,b,y);

input clk;
input a,b;
output reg[1:0] y;

always@(posedge clk)
begin
        $display("hello razak");
        y = a+b;
        $display("a = %0d, b = %0d, y = %0d",a,b,y);
        $finish;
end
endmodule
 

TestBench in SystemC

      #include "Vadd.h"
   
  6 int sc_main(int argc,char** argv) {
  7         Verilated::commandArgs(argc,argv);
  8         sc_clock clk{"clk",10,SC_NS,0.5,3,SC_NS,true};
  9         sc_signal<bool> a;
 10         sc_signal<bool> b;
 11         sc_signal<sc_uint<32>> y;
 12
 13         Vadd* top = new Vadd("top");
 14         top->clk(clk);
 15         top->a(a);
 16         top->b(b);
 17         top->y(y);
 18 
 19 
 20         while(!Verilated::gotFinish()){
 21                 sc_start(1,SC_NS);
 22                 // Open VCD file
 23                 sc_trace_file *wf = sc_create_vcd_trace_file("add");
 24                 // Dump the desired signals
 25                 sc_trace(wf, clk, "clk");
 26                 sc_trace(wf, a, "a");
 27                 sc_trace(wf, b, "b");
 28                 sc_trace(wf, y, "y");
 29                 sc_start(100,SC_NS);
 30                 cout<<"hi"<<endl;
 31         }
 32         delete top;
 33         return 0;
 34 }
I'm trying to run the above code on Verilator 3.916 2017-11-25  and g++ (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0 compiler.

When I run add.v verilog file and sim_main.cpp on verilator with the following command I'm getting error has "sim_main.cpp:17:10: error: no match for call to ‘(sc_core::sc_out<unsigned int>) (sc_core::sc_signal<sc_dt::sc_uint<32> >&)’
  top->y(y); "

commands:

verilator -Wall --sc --exe sim_main.cpp add.v
make -j -C obj_dir -f Vadd.mk Vadd
obj_dir/Vadd

[Eyck]

Verilator generated a port having a datatype of unsigned int. You try to bind it to a signal having a data type of sc_uint<32>. This is not possible. Either you declare y in sc_main as sc_signal<unsigned> or you instruct verilator to use sc_uint for its ports by passing '--pins-sc-uint' as command line argument.

[Abdul Razak H S]

Thank You Eyck it's working