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Transaction adapter for RAL model for converting bus item to axi and vice versa

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Hi sacjin1123 , did you use the cadence UVC for AXI ?


We are also using the cadence UVC for AXI. I made a reg2_axi_adapter just like the apb example in the user guide by replacing apb_rw with vr_axi::vr_axi_master_burst.

There are however, 2 issues with the burst_reads and burst_writes:

1. There is a bug with burst reads where the value needs to be changed to an inout (there are examples in the forum).

2. The uvm_reg_map::do_bus_write and uvm_reg_map::do_bus_read breaks bursts into single transfers. While there may be a better way, I added a frontdoor to the map I using so I could bypass the map's do_write and do_read.

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I think [/url]http://www.eda.org/svdb/view.php?id=4046 gives some of the information I was talking about. Specifically:

3) In uvm_mem.svh, the uvm_reg_item rw does not have its value field set, which means it is fixed at size 1 by the constructor. It should be set to the value array argument. That argument is an output, however, so you can't just assign it to rw.value. I think the argument should be inout, so that it can be assigned to the value field and thus set the size of the burst operation.

The changes I made were:

line 1542, change output to inout

line 1564 add rw.value = value;

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I think [/url]http://www.eda.org/svdb/view.php?id=4046 gives some of the information I was talking about. Specifically:

Hi timcaputo

Today i came across a different problem. (maybe it is problem number 2 explained by you about the single transfers).I m using an AXI interface of width 32 bits and i have to write to registers of varying widths (32,64,128 and 256).

i)Write to 32 bit register works, read for 32bit registers occurs without any at the interface level but does not get reflected at the output of the read task.It is always 0. ( i have set length =1 ,axi_burst.length =length , axi_burst.transfers[] = new[length]

and a for loop for constructing the transfer class, axi_burst.transfers = new(); where i =0 to length-1 )

ii)Write to a 64 bit register also works, but it occurs in two bursts. I have set length =2 which should initiate two transfers in the same burst.

But it happens in two bursts, i can see two awvalids for two addresses.

The read also happens in two bursts, each consisting of two transfers and thus results in an error.

Can you please help me with an example code or do you have an idea on how the settings should be?

I m especially confused with the bus2reg function.

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