systemc issue

[shiva25]

How can the value of port change automatically after 1 clock cycle.   what should i do for this?

[Eyck]

You need to implement a method or a thread being sensitive on the clock. Something like:

SC_MODULE(test) {
  sc_core::sc_in<bool> clk_i{"clk_i"};
  sc_core::sc_ou<bool> out_o{"out_o"};

  SC_CTOR(test) {
	SC_THREAD(run);
  }
  
  void run(){
    while(true) {
      wait(clk_i.posedge_event());
      out_o.write(!out_o.read());
    }
  }
};