Modeling three-state gates

[katang]

I am attempting to model a three-state system in SystemC, adapting the biological behavior to gates. (The idea is similar to neuron synapses' biological behavior: I want to use pulses instead of levels.) Say, by default a two-input gate has its both inputs (synapses) and its output (axon) in state Z. If a 'spike' arrives (an event) to one of its inputs, for the duration of the spike, the input is set to 0 or 1 (as received) for a while, then the input changes back to Z. The gate remembers its inputs, and when it receives its second input, it sets its output to the calculated value for a while, then it changes back to Z (and resets input latching). Is this synthesizable? Can its 'real estate' demand be estimated? (How much such a solution increases number of gates in the circuit?) I.e. the level sequence is Z-0/1-Z, instead of 0-1-0.

[Eyck]

tri-state logic is not synthesizable. But if you use a 2-bit vector where one bit shows activity and one bit the value this can be synthesized...

But it doubles the number af wires and depending on the gate logic the size of the logic. This may be wroked around by designing a custom cell for the standard cell library. After it is characterized the cell might be used by the synthesizer.