RISC CPU example

[scsc]

Realized after digging into the old risc-cpu example coming with systemc's installation that the example wasn't complete. For example, the code seemed containing some cache coherence protocols like MESI. But there was no implementation for that except some printf() statements. Same as the branch prediction unit. So just wonder if there are more comprehensive example out there? 

[maehne]

The group of Daniel Große from University of Bremen and now Johannes Kepler University in Linz has released a RISC-V-based virtual prototype under MIT license, which could be of interest for you.

[Eyck]

There are quite few more RISC-V ISS/VPs, all based on SystemC. E.g.:

• ETISS of TU München (https://github.com/VP-Vibes/etiss)
• TGC-VP of MINRES (https://github.com/VP-Vibes/TGC-VP)

 

[scsc]

Thanks Guys for the links!

[scsc]

@Eyck,

Looking at the GitHub you provided, what's the instructions to generate RTL and verification test cases? I am not familiar with what TGC cores are. Does the RTL and verification generation come with the libraries in these TGC core libraries? I think the Vibes are just for the interconnects like AXI, maybe for the cores. 

[Eyck]

TGC is 'The Good Core' family of RISC-V cores of MINRES Technolgis GmbH. The VP-Vibes organization at Github is for any project related to Virtual Prototypes. So the SystemC-Components library comes with SystemC utilities, components like register and generic bus targets as well as on-chip interconnect protocol definitions. The VPV-Peripherals provides peripherals which can be used in building VPs while the TGC-VP assembles all these components into a VP.

Parts of the VP, in detail the ISS and its infrastructure, is being used as reference model to verify the RTL implementation(s). For this we use an insturction stream generator and a response checker (see also here).

[scsc]

Thanks Eyck again for these pointers. Much clearer now on the structures.