Problem with Register model

[paragsathe]

Hi,

I am having an issue with Regsiter access layer.

I am doing the following in my register read write sequence.

1) Declaring a handle to Register model

reg_model_type handle_rm;

2) Declaring a uvm_reg dynamic array and a couple of data items

uvm_reg temp_access_regs[$];

rand uvm_reg_data_t data;

uvm_reg_data_t ref_data;

3) In body task, i am assigning reg. model to the dynamic array like this

handle_rm.get_registers(temp_access_regs);

4) Furthur in the sequence, i am writing values to register bank, shuffling registers, reading back the written values and asserting uvm_error if the values dont match.

foreach(temp_access_regs[k])

temp_access_regs[k].write(status,data,.parent(this));

temp_access_regs.shuffle();

foreach(temp_access_regs[j])

begin

ref_data = temp_access_regs[j].get();

temp_access_regs[j].read(status,data,.parent(this));

end

But the problem i am getting is the get() is returning wrong value. After debugging i found that the mirror values are getting modified with some other register values without me actually writing to them. So the checks are failing. I double checked that i am not doing set or write anywhere else.

Why is this happenning?

Can anybody help me to solve this issue

Thanks.

Parag