Accessing a memory element inside a memory model.

[bap001]

Hi all,

I am trying to access a sparse memory array inside a memory model instantiated in the top level verilog TB. I am trying to see if I ahve the correct UVM code , to access this memory from say a sequence. Any help would be much appreciated.

So, this is what I have :

//***************************

//Verilog side

1.module tb ();

//Has DUT instance - that writes to the DDR memory model

//This is the meory model

ddr3_model u_ddr3

endmodule

2.Inside ddr3_model :

//Lets say we have this :

static reg [15:0] mod_mem [1024];

//***************************

//Now on the UVM side

1. I have this in the env :

ddr3_mem_model_c ddr3_mem_model;

In the build of the env :

if (ddr3_mem_model == null) begin

ddr3_mem_model = ddr3_mem_model_c::type_id::create("ddr3_mem_model");

ddr3_mem_model.build();

ddr3_mem_model.lock_model();

ddr3_mem_model.set_hdl_path_root("tb.u_ddr3");

end

2.The uvm memory and mem_model;

a.class ddr3_mem extends uvm_mem;

`uvm_object_utils(ddr3_mem)

function new(string name = "ddr3_mem");

super.new(name, 32'h400, 16, "RW", UVM_NO_COVERAGE);

endfunction // new

//------------------------------------------------------

function void set_hdl_slices();

this.clear_hdl_path("ALL");

//If I do this - WILL IT WORK?

this.add_hdl_path_slice("mod_mem", 0, 16);

endfunction : set_hdl_slices

endclass // ddr3_mem

b.//The mem_model in uvm

class ddr3_mem_model_c extends uvm_reg_block;

`uvm_object_utils(ddr3_mem_model_c)

ddr3_mem ddr3_mem_inst;

//----------------------------------------

function new(string name = "ddr3_mem_model_c");

super.new(name, UVM_NO_COVERAGE);

endfunction // new

//----------------------------------------

virtual function void build();

ddr3_mem_inst = ddr3_mem:: type_id::create("ddr3_mem_inst");

ddr3_mem_inst.configure(this, null, "");

ddr3_mem_inst.build();

this.set_hdl_slices();

endfunction // build

//------------------------------------------------------

function void set_hdl_slices();

this.clear_hdl_path("ALL");

this.add_hdl_path("", "RTL");

ddr3_mem_inst .set_hdl_slices();

endfunction // set_hdl_slices

endclass // v3_ddr3_mem_model_c

Question :

If I do the above, is it enough , to read /write the memory element in the seq lib? I have used the register model to access registers in the DUT and that works fine. However, to access the memory in the way I want to, my gut is that I am missing something - what I have does not seem right/adequate - so just want to confirm. I am also compiling this in parallel.. but want to get this thread going.

Any help/inputs/thoughts would be highly appreciated. Thanks in advance.

Thanks a lot!

[bap001]

Also, can we access memory via backdoor at all? Are there any UVM examples on this? The example ( mem_example) given contains only frontdoor accesses?

Thanks !