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Is there solution can implement the reverse operation of set_rate() ?


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I implemented two modules in the SystemC-AMS: A and B.

The time step of A module is 1s, while the time step of B is 60s.

I use set_rate(60) function to read the output from A as the input of B, but I also want input of A(1s time step) can read the output of B(60s time step). 

Since I cannot set_rate(1/60), is there any solution? 

 

Thanks a lot.

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Yes, you'll need to add a helper module C, which upsamples your slow signal to the fast rate, i.e., which input rate is 1 and output rate is 60. In the simplest case, you can just duplicate 60 times the same value. However, you may also implement some kind of interpolation. Note: By creating a feedback loop, you will also have to specify a suitable delay and initial samples to restore causality!

I suggest that you read the section 2.1 "Modeling fundamentals" of the the SystemC AMS User's Guide to gain further insight.

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