BigSteve Posted August 31, 2018 Report Share Posted August 31, 2018 Hi all, I use SystemC quite extensively to validate verilated SystemVerilog code. Verilator, produces a SystemC wrapper around a model that when evaluated behaves like the equivalent SystemVerilog RTL. Within the context of my surrounding verification environment, I instantiate the Verilated module and clock it. My associated SystemC is driven off this same clock and consists of a range of SC_METHODS and SC_THREADS. At present, to sample the output of my Verilated module, I am forced to introduce a very small delay after the rising edge of the clock to ensure that the SystemC environment evaluates after the Verilated module. Without this small delay, the SystemC will often sample stale state before it evaluates before the Verilated module. I understand that in an event-driven model such as SystemC it is not possible to determine the order in which proceses evaluate, you may recall however from SystemVerilog that a "program" scope exists where a UUT can be evaluated before the surrounding code evaluates. This avoids the sequencing issues between RTL and the TB, and drastically simplifies the code. My question is this: what is the established technique to achieve the same behavior in SystemC? Is there a more sophisticate synchronizing scheme other than simply introducing some arbitrary sampling delay? Steve Quote Link to comment Share on other sites More sharing options...
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