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  1. Hi, UVMSC fails to compile of OSX with the error message below. The "macros" archive contains no symbols (just seems to be a macro definitions), so it shouldn't be compiled into an archive. Making all in conf make[4]: Nothing to be done for `all'. Making all in dpi make[4]: Nothing to be done for `all'. Making all in factory make[4]: Nothing to be done for `all'. Making all in macros CCLD libmacros.la ar: no archive members specified usage: ar -d [-TLsv] archive file ... ar -m [-TLsv] archive file ... ar -m [-abiTLsv] position archive file ... ar -p [-TLsv] archive [file ...] ar -q [-cTLsv] archive file ... ar -r [-cuTLsv] archive file ... ar -r [-abciuTLsv] position archive file ... ar -t [-TLsv] archive [file ...] ar -x [-ouTLsv] archive [file ...] make[4]: *** [libmacros.la] Error 1 make[3]: *** [all-recursive] Error 1 make[2]: *** [all-recursive] Error 1 make[1]: *** [all] Error 2 make: *** [all-recursive] Error 1
  2. Roman, Thanks for your reply. It would appear that at some point the notion of PHASE_CALLBACK was introduced into SystemC as an experimental feature. This would appear to be the precise feature that I am looking for. It allows for callbacks to be introduced that are then called on the various simulator phases (before_timestep, update_done, simulation_paused). It would appear that the update_done phase callback could be used to sample all the Verilated module outputs. This is in sc_simcontext.cpp. Will this ever been introduced into SystemC, or will it always remain an experimental feature?
  3. Basarts, this is indeed a very valid solution; however, I am more interested in the correct, canonical method - I've always viewed this approach as a bit of a hack. Roman: Consider two processes, clocked from the same clock. One a Verilated module; Two some sampler that samples the output of the Verilated module. If Two runs before One, Two sees the old data. Is there no way to enforce that One be evaluated before Two? It appears that SystemC has no notion of this; whereas SystemVerilog does.
  4. Hi all, I use SystemC quite extensively to validate verilated SystemVerilog code. Verilator, produces a SystemC wrapper around a model that when evaluated behaves like the equivalent SystemVerilog RTL. Within the context of my surrounding verification environment, I instantiate the Verilated module and clock it. My associated SystemC is driven off this same clock and consists of a range of SC_METHODS and SC_THREADS. At present, to sample the output of my Verilated module, I am forced to introduce a very small delay after the rising edge of the clock to ensure that the SystemC environment evaluates after the Verilated module. Without this small delay, the SystemC will often sample stale state before it evaluates before the Verilated module. I understand that in an event-driven model such as SystemC it is not possible to determine the order in which proceses evaluate, you may recall however from SystemVerilog that a "program" scope exists where a UUT can be evaluated before the surrounding code evaluates. This avoids the sequencing issues between RTL and the TB, and drastically simplifies the code. My question is this: what is the established technique to achieve the same behavior in SystemC? Is there a more sophisticate synchronizing scheme other than simply introducing some arbitrary sampling delay? Steve
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