Jump to content

event vs software call

Recommended Posts

I'm learning systemc now, my systemc book says,

Transaction-level modelling: avoid events as much as possible: use intermodule software call.

I am not clear with the concept of event and intermodule software call. Does events means event-based, is it the conventional approach we used for hardware modelling, like in systemverilog? Why do transaction level modelling use software call instead of event?

Thank you very much!

Link to post
Share on other sites

SystemC is an event based simulator as VHDL or (System)Verilog simulators are. So you would write to signals, the update their values and notify an event for that so that processes can react on them. This is described in the SystemC standard, I guess paragraph 4.2 Simulation.
The downside of this that each event and the evaluation of processes being triggered by this takes time. As the processes are often fairly short this incures a significant overhead and speed impact.

In TL modeling you forward the function calls via a port/export directly to the affected/addressed module/function. This way a lot of context switches can be avoided and the simulation speed is higher. But since the effect (e.g. writing a register) happens immediately care needs to be taken to not introduce feedback loops and a like which won't happen if you use signales and events. To model timing you also carry some delay time with the transaction so that the functions along the call chain and the target function can tell the initiator of the transaction how long the entire transaction took.

Best is to have a look into the examples coming with TLM2.0 (now being part of the SystemC distribution), also Doulos has some explanation and examples: https://www.doulos.com/knowhow/systemc/tlm2/

Best regards

Link to post
Share on other sites


Thank you for your answer. I read the Doulos tutorial, and built a TLM model for a simple RISC-V processor. I still didn't quite see the difference. In systemc, builder uses the functions under tlm_generic_payload class to bind different modules, in systemverilog, builder uses a top module to bind the port of each module together, which for me doesn't seem too different. There is no event-based or conditional trigger between modules in systemverilog. As to the event within the module, systemc does that too (for example, in the first example code from Doulos, they use for loop to generate data, or you may use other conditional statements or fstream object, which are also events).

So where does I get wrong?

Thank you very much!

Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...