Jeferson Posted March 15, 2018 Report Share Posted March 15, 2018 Hello everyone, I'm performing the verification of a simple Sample and Hold implemented in SystemC-AMS. The Sample and Hold is modeled with the MOC ELN, the MOC TDF input signal source, and Sample and Hold output a port for the discrete domain. When the sample switch is closed for a long time the circuit has a low pass filter behavior, so the check consists of finding the cut-off frequency in this situation through the voltage gain (v_out / v_in = 0.707). However, this gain is only being achieved with frequencies much larger than the cutoff frequency. Codes are shown below Can anyone help? The V_in and Vout measurements are made by the read () method on the input signal "sc_core :: sc_signal <double> adc_in_source" and "sc_core :: sc_signal <double> adc_out". Thank you in advance. #include <systemc-ams.h>#include <cmath> class sample : public sc_module { public: sca_tdf::sca_in < bool > ctrl_lp; // CAPCOM input for the switch sc_in < double > in_src; // Analog signal input from the MUX sc_out < double > out; // Sampled signal output sca_eln::sca_tdf_rswitch key; // Switch ideal. Simulates sample switching. sca_eln::sca_node n1,n2,n3,n4; // electrical nodes sca_eln::sca_node_ref gnd; sca_eln::sca_c CI; // Low-pass filter input capacitance sca_eln::sca_r RI; // Internal filter resistance low pass filter sca_eln::sca_r RS; // External source resistance sca_eln::sca_de::sca_vsource vin_src; sca_eln::sca_de::sca_vsink vout; sample(sc_module_name name) : sc_module(name) , CI("CI") , RI("RI") , vin_src("vin_src") , vout("vout") , RS ("RS") , key("key") { vin_src.inp(in_src); vin_src.p(n1); vin_src.n(gnd); RS.value = 0e3; RS.n(n1); RS.p(n2); RI.value = 2e3; RI.n(n2); RI.p(n3); key.p(n4); key.n(n3); key.ctrl(ctrl_lp); key.ron; key.roff; CI.value = 40e-12; CI.q0 = 0.0; CI.p(n4); CI.n(gnd); vout.outp(out); vout.p(n4); // Vout.tdf_voltage(out); vout.n(gnd); } ~sample(){} }; #ifndef SRCS_H #define SRCS_H # include <systemc-ams.h> SCA_TDF_MODULE (srcs) { sca_tdf::sc_out<double> out_tdf_de; // output port srcs( sc_core::sc_module_name nm, double ampl_, double freq_, sca_core::sca_time Tm_) : out_tdf_de ("out_tdf_de") , ampl(ampl_) , freq_1(freq_) , Tm(Tm_) {} void set_attributes(); void processing(); public: double t; double ampl; // amplitude double freq_1; // frequency double data;// setup_param; int setup; sca_core::sca_time Tm; // module time step }; #endif // srcs_H #include "srcs.h" #include <cstdlib> /// for std::rand #include <cmath> void srcs::set_attributes() { set_timestep(Tm); } void srcs::processing(){ t = out_tdf_de.get_time().to_seconds(); // Get current time of the sample data = (ampl/2)*sin((2.0 * M_PI * freq_1 * t)) + ((ampl/2)); out_tdf_de.write(data); // Write value on output } Quote Link to comment Share on other sites More sharing options...
maehne Posted March 19, 2018 Report Share Posted March 19, 2018 Yes, in SystemC AMS, as in other analog/mixed-signal simulators, good precision usually requires the setting of a small enough simulation time step. As a rule of thumb, you should set the time step in a cluster of connected TDF/ELN/LSF modules such that the signal with the highest occurring spectral frequencies is sampled with at least 5 to 10 samples per period of the highest frequency for moderate accuracy and about 20 samples per period for good accuracy. Does your configured module time step respect this with respect to the cut-off frequency and selected input signal? For best simulation performance, you module srcs and sample should be connected via TDF ports and TDF signals and not via TDF<->DE converter ports and DE signals. Then, you can profit from the fact that the srcs and sample module will end up in the same static TDF schedule, which is executed by the SystemC AMS simulation kernel. I would also recommend that you don't include the SystemC/SystemC-AMS headers using <systemc.h> and <systemc-ams.h> as this pollutes the public namespace. Instead, prefer the recommended headers <systemc> and <systemc-ams>. Quote Link to comment Share on other sites More sharing options...
Jeferson Posted March 19, 2018 Author Report Share Posted March 19, 2018 4 hours ago, maehne said: Yes, in SystemC AMS, as in other analog/mixed-signal simulators, good precision usually requires the setting of a small enough simulation time step. As a rule of thumb, you should set the time step in a cluster of connected TDF/ELN/LSF modules such that the signal with the highest occurring spectral frequencies is sampled with at least 5 to 10 samples per period of the highest frequency for moderate accuracy and about 20 samples per period for good accuracy. Does your configured module time step respect this with respect to the cut-off frequency and selected input signal? For best simulation performance, you module srcs and sample should be connected via TDF ports and TDF signals and not via TDF<->DE converter ports and DE signals. Then, you can profit from the fact that the srcs and sample module will end up in the same static TDF schedule, which is executed by the SystemC AMS simulation kernel. I would also recommend that you don't include the SystemC/SystemC-AMS headers using <systemc.h> and <systemc-ams.h> as this pollutes the public namespace. Instead, prefer the recommended headers <systemc> and <systemc-ams>. Hi maehne, thank you very much for the answers. 1) Yes, my time step is set in srcs (Tm_ = 1e-9) and the expected cut-off frequency is approximately 2MHz. 2) I was able to find the expected cutoff frequency with good accuracy, even with the TDF-> DE domain conversion ports, but I will change to achieve better results as you indicated !! The error was in my analysis, because the input sinusoid had an off set DC which changes the shape to find the cutoff frequency, but I have already solved it. 3) Yes I will follow the instructions to use the recommended headers. Quote Link to comment Share on other sites More sharing options...
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